Shifted Gate Contact Layout for Short-Resistant Cross-Coupled Cells
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Solution Overview
Problem
As semiconductor device dimensions shrink, the risk of short circuits between gate and source/drain contacts increases due to limited space and competing demands for efficient wire routing, complicating gate and gate contact placement.
Innovation Solution
Reconfigure gate contacts by offsetting them from the centerline to increase spacing with source/drain contacts, allowing for a two-contacted poly pitch (CPP) design that minimizes shorting risks and optimizes space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate contacts are positioned at the centerline of gates, then wiring symmetry is maintained, but spacing between gate contacts and source/drain contacts decreases increasing short circuit risk
Solution Approach 1:
The gate contact is positioned asymmetrically relative to the gate centerline, specifically offset toward one side to increase the distance between the gate contact and the source/drain contact. This asymmetric placement resolves the short circuit risk by creating unequal spacing where the critical gap between gate and source/drain contacts is maximized, rather than maintaining symmetric centerline alignment.
2Productivity
If device dimensions are shrunk to increase density, then productivity is improved, but space between gate and source/drain contacts decreases leading to increased short circuit failures
Solution Approach 1:
The contact placement strategy applies local quality by differentiating the spacing requirements in different regions. Specifically, the gate contact is positioned to create adequate spacing in the critical region between gate and source/drain contacts, while other regions can maintain tighter pitch for density. This localized optimization allows high density overall while preserving reliability in the vulnerable gap region.
3Reliability
If gate contacts are offset from centerline, then spacing to source/drain contacts increases reducing shorts, but wire routing efficiency decreases
Solution Approach 1:
The offset gate contact placement utilizes the lateral dimension along the gate length to achieve the spacing benefit, rather than requiring additional vertical routing layers or complex three-dimensional wiring. By adjusting the contact position along the gate's longitudinal axis, the design maintains planar routing simplicity while achieving the necessary electrical isolation.
Data Source
AI summary
A semiconductor device includes a first diffusion region having a longitudinal axis and a second diffusion region parallel with the first diffusion region. A source/drain contact contacts the first diffusion region and the second diffusion region. A gate has a centerline in a transverse direction to the longitudinal axis. A gate contact connects to the gate at a position that has an offset from the centerline away from the source/drain contact.