Shifted VBPR Contact Layout With Asymmetric S/D Spacers
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Solution Overview
Problem
The increasing device density in semiconductor processing for IC chips strains the design and fabrication of interconnects, particularly in delivering power from buried power delivery networks to front-end devices, making it challenging to integrate power delivery networks effectively.
Innovation Solution
A semiconductor structure with a shifted via backside power rail (VBPR) structure that includes a dielectric via preventing electrical contact to adjacent FET devices, allowing for asymmetric S/D sidewall spacers and a shifted VBPR connection to the sidewall of one FET device, maintaining sufficient metal volume for robust power delivery while allowing for more advanced technological nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device density is increased to improve integration, then productivity is improved, but manufacturing precision deteriorates due to strain on interconnect design and fabrication
Solution Approach 1:
The patent introduces a shifted VBPR structure where the via backside power rail is positioned asymmetrically relative to adjacent FET devices. This dimensional shift in the power rail positioning allows for asymmetric S/D sidewall spacer design, which provides additional design freedom to maintain manufacturing precision while supporting higher device density by optimizing interconnect spacing and alignment tolerances.
2Area of moving object
If asymmetric S/D sidewall spacers are used to reduce space requirements, then area is reduced, but device complexity increases
Solution Approach 1:
The patent employs asymmetric S/D sidewall spacers with different dimensions on opposite sides of the source/drain structures. This asymmetry is enabled by the shifted VBPR configuration, which provides different spacing requirements on each side. The asymmetric design reduces overall area by optimizing spacer placement and dimensions, while the shifted VBPR structure absorbs the added design complexity through its flexible positioning capability.
3Reliability
If shifted VBPR structure with dielectric via is implemented to prevent short circuits, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent introduces a dielectric via as an intermediary element within the shifted VBPR structure. This dielectric via acts as an electrical isolation barrier that prevents short circuits between the power rail and adjacent FET devices. While this adds structural complexity, the shifted VBPR configuration allows the dielectric via to be positioned optimally for maximum isolation effectiveness, and the asymmetric spacer design compensates for the added complexity by providing clear spatial separation.
4Power
If metal volume is maintained for robust power delivery, then power delivery performance is improved, but area is increased
Solution Approach 1:
The patent applies local quality optimization by concentrating metal volume strategically within the shifted VBPR structure. The asymmetric S/D sidewall spacers enable different metal dimensions and configurations on each side of the power rail, allowing robust power delivery performance to be achieved in regions requiring high current capacity while minimizing metal volume in areas where lower power density is sufficient. This localized optimization maintains overall power delivery robustness while reducing total metal area.
Data Source
AI summary
A semiconductor structure including first and second FET devices and a method of forming the structure. A first FET is formed with a first source/drain structure and a second FET is formed with a second source/drain structure. A via backside power rail (VBPR) metal contact structure is formed between the first FET device and the second FET device, the VBPR contact structure having a first portion contacting an underlying backside power rail and a second via portion electrically contacting only a sidewall of the first source/drain of the first FET device. The first portion of the VBPR contact structure contacting the backside power rail is of a first width and the second via portion of the VBPR contact structure contacting only a sidewall of the source or drain of the first FET device is of a second width, the first width greater than the second width.