Shifting Register Single Latch Narrow Frame Panel Design
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Solution Overview
Problem
Conventional low-temperature-polycrystalline-silicon shifting registers require multiple gate circuits and complex circuit compositions, making them unsuitable for achieving a narrow frame panel due to increased layout space and circuit complexity.
Innovation Solution
A shifting register design utilizing a single latch and transmission gate, with specific TFT configurations and inverter connections, allows the transmission gate to remain on or off, enabling signal shifts by selectively inputting a clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LTPS shifting registers use multiple D-triggers and transmission gates, then signal latching and shifting functions are achieved, but circuit complexity increases and layout space expands
Solution Approach 1:
The patent combines two D-triggers and their associated transmission gates into a single latch unit. The latch uses two cross-coupled inverters with transmission gates controlled by complementary clock signals, integrating the latching function that previously required separate D-trigger stages. This merging reduces the number of discrete components while maintaining the essential signal latching and shifting functionality.
Solution Approach 2:
The simplified latch circuit serves multiple functions: it acts as a D-trigger for signal latching, provides signal delay through the transmission gate timing, and enables signal shifting when cascaded. By making the latch unit multi-functional, the patent eliminates the need for separate D-trigger and transmission gate components, thereby reducing overall circuit complexity while preserving all necessary operations.
2Reliability
If conventional shifting registers use two D-triggers per stage, then signal shifting is achieved, but layout space increases
Solution Approach 1:
The patent merges the functionality of two D-triggers into a single latch structure with cross-coupled inverters and shared transmission gates. This consolidation reduces the physical footprint by eliminating redundant components such as separate transmission gates and inverters for each D-trigger, while maintaining the signal shifting capability through the cascaded latch architecture.
Solution Approach 2:
The latch circuit employs a nested structure where transmission gates are embedded within the inverter feedback paths, and clock control signals are nested within the same gate structure. This nesting allows multiple functions (latching, delaying, shifting) to be implemented within a compact area by sharing common components rather than duplicating them.
Data Source
AI summary
A shifting register, a gate driving apparatus and a display apparatus comprising the shifting register. The shifting register comprises a latch (21), a transmission gate (22), a first TFT (T1), a second TFT (T2), a third TFT (T3) and a first inverter (23), the first TFT (T1), having a gate connected to a reset (Reset) of the shifting register, a drain connected to a drain of the second TFT (T2) and an input (M) of the latch (21) respectively; the second TFT (T2), having a gate connected to an input (Input) of the shifting register, the third TFT (T3), having a gate connected to the inverting output of the latch (21), a drain connected to an input of the first inverter (23); an output of the transmission gate being connected to a drain of the third TFT (T3), an input of the transmission gate being connected to a clock signal input (CLOCK); the drain of the third TFT (T3) being connected to a non-inverting output (Output_Q) of the shifting register, an output of the first inverter being connected to an inverting output (Output_QB) of the shifting register. The shifting register achieves a signal shift with only one latch (21).