Shmoo Delay Circuit for CDC and RDC Metastability Detection
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Solution Overview
Problem
In integrated circuits and system-on-a-chip (SoC) designs, metastability conditions often arise at clock domain crossings (CDCs) and reset domain crossings (RDCs), making it difficult to detect these issues during the design phase, and correcting them post-manufacture can be costly and impractical.
Innovation Solution
The implementation of a controllable shmoo delay circuit that allows for varying the delay of asynchronous reset and clock signals, enabling the identification of metastability conditions during the design phase and allowing for optimal delay settings to be determined and applied.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed delay paths are used in reset and clock domains, then circuit operation is simple, but metastability conditions cannot be detected during design phase
Solution Approach 1:
The patent implements dynamic delay adjustment by replacing fixed delay paths with controllable delay elements that can be programmed during testing. The delay amount is made variable through control signals, allowing the system to sweep through different delay values to detect metastability conditions while maintaining simple fixed delays during normal operation.
Solution Approach 2:
The patent changes the delay parameter from a fixed physical value to a programmable value that can be adjusted during testing. By modifying the delay parameter dynamically, the system can create various timing scenarios to expose metastability issues without permanently increasing circuit complexity.
2Reliability
If metastability conditions are detected late at silicon validation, then PVT characterization can identify issues, but corrections become extremely costly requiring silicon re-design
Solution Approach 1:
The patent performs preliminary testing during the design phase by incorporating delay sweep functionality that can be executed before silicon manufacture. This allows timing violations and metastability conditions to be detected early, enabling corrections to be made during the design phase rather than requiring costly post-manufacturing re-design.
Solution Approach 2:
The patent implements self-testing capability within the circuit itself, where the delay sweep and metastability detection are performed automatically during the design phase without requiring external testing equipment. This self-service approach enables early detection and correction of timing issues.
3Reliability
If delay sweep functionality is implemented, then metastability conditions can be exposed, but additional test circuitry and control mechanisms are required
Solution Approach 1:
The patent designs the delay sweep circuitry to serve multiple functions: it can be used during design phase testing to detect metastability conditions, and the same circuitry can potentially be used for calibration and optimization during operation. This multi-functionality reduces the overall complexity by reusing the same hardware for multiple purposes.
Solution Approach 2:
The patent introduces a control signal as an intermediary that manages the delay sweep operation. This control signal coordinates the delay element adjustments and the testing process, allowing the complex delay sweep functionality to be managed through a simple control interface rather than requiring complex hardwired logic.
4Manufacturing precision
If asynchronous reset and clock signals are shmooed with variable delays, then optimal delay settings can be determined, but the circuit requires programmable delay elements
Solution Approach 1:
The patent segments the delay path into multiple discrete delay elements that can be individually controlled. By dividing the total delay into segments, the system can achieve fine-grained delay adjustment through simple selection of individual segment combinations, reducing the complexity compared to using a single programmable delay element.
Data Source
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AI summary
A first circuit path communicates a first, asynchronous, signal, and a second path communicates a second signal. A schmoo delay circuit receives the first and second signals and includes shmoo control circuitry and a delay generator. The delay generator receives a delay selector signal from the shmoo control circuitry indicative of an amount of delay. The shmoo delay circuit provides a delayed version of at least one of the first or second signals. A first logic circuit receives the delayed version of the at least one of the first signal or the second signal, and a second logic circuit receives another one of the first signal or the second signal. The shmoo control circuitry modifies the delay selector signal to sweep through a set of different delay amounts applied by the delay generator to generate delayed versions of the at least one of the first signal or the second signal.