Detecting Shoot-Through Timing Failures in Semiconductor Scan Chains
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Solution Overview
Problem
Detecting and locating shoot-through timing failures in scan chains of semiconductor integrated circuits is challenging due to complex anomalies in scan test output data and the difficulty in identifying and correcting defects in clock nets or buffers.
Innovation Solution
The method involves programmatically determining shoot-through locations using reset pattern analysis and physical clock skew analysis to identify delayed cells and their associated clock nets, allowing for the identification and correction of defects in the semiconductor design and fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan chains are used for testing semiconductor integrated circuits, then testing capability is improved, but detecting and locating failures becomes particularly challenging
Solution Approach 1:
The patent divides the scan chain into multiple segments by identifying candidate shoot-through locations at clock branch points. Each segment can be independently analyzed, transforming the complex problem of locating failures in a long scan chain into manageable segments, thereby reducing the difficulty of detecting and locating failures while maintaining testing capability.
2Reliability
If multiple shoot-through cells exist in a single scan chain, then timing failure detection becomes more complex, but comprehensive coverage is improved
Solution Approach 1:
The patent introduces an intermediary analysis layer that processes scan chain output data to identify shoot-through locations. This intermediary layer transforms complex anomalies from multiple shoot-through cells into identifiable patterns, allowing comprehensive coverage of timing failures while reducing the apparent complexity of the anomalies through systematic analysis.
3Measurement precision
If clock delay or skew causes shoot-through timing failures, then data integrity is compromised, but identifying the specific clock net or buffer causing the delay is difficult
Solution Approach 1:
The patent performs preliminary analysis to identify candidate shoot-through locations at clock branch points before conducting detailed failure analysis. By pre-identifying potential problem areas where clock delay or skew is most likely to occur, the system prepares the groundwork for faster and more precise identification of the specific clock net or buffer causing the delay, thereby improving measurement precision while reducing the difficulty of clock defect identification.
Data Source
AI summary
“Shoot-through” timing failures in a scan chain of a defective semiconductor integrated circuit corrupt test pattern data used to perform failure analysis. Methods and procedures are provided to detect “shoot-through” conditions, determine the number of shoot-through scan cells, and to determine the location of the shoot-through cells within a scan chain. Reset test pattern results can be analyzed to identify candidate locations of shoot-through cells and when combined with candidate cell locations from analysis of physical clock distribution trees and potential clock-skew issues, the exact location of all shoot-through cells can be determined. Methods are also provided to use shoot-through cell locations to identify the defective clock net containing the physical defect causing the clock skew conditions needed to produce shoot-through timing failures.