Short-Circuit Protection Circuit for Positive Output Hold

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Solution Overview

Problem

Existing semiconductor devices with overcurrent protection fail to maintain positive voltage and current values at the output terminal when short-circuited, risking damage or malfunction, especially when connected to loads with inductance.

Innovation Solution

Incorporating a short-circuit protection circuit with a timing generator to rapidly discharge the output node and disable the overcurrent protection circuit temporarily, followed by enabling it to regulate current and voltage to safe levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional overcurrent protection circuit is used, then overcurrent can be detected, but the output voltage and current cannot be maintained at positive values during short-circuit conditions

Engineering Contradiction:
Improveovercurrent protection capabilityVSAvoidnegative voltage and current at output terminal
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The timing generator proactively activates the discharge transistor before the overcurrent protection circuit can drive the output to negative values. This preliminary action counteracts the harmful effect by removing excess charge from the output node, preventing the voltage and current from becoming negative during short-circuit conditions.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The timing generator acts as an intermediary between the overcurrent detection and the discharge control. It receives the overcurrent signal and generates a timed control signal that activates the discharge transistor for a specific duration, mediating the response to prevent negative output values while maintaining protection functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If the discharge transistor is activated continuously to prevent negative output values, then output voltage and current remain positive, but the device cannot supply power to normal loads

Engineering Contradiction:
Improvepositive voltage and current maintenanceVSAvoidpower supply capability to loads
Core Design Contradiction:
Object-affected harmful factorsVSProductivity

Solution Approach 1:

The discharge transistor is activated periodically only when needed - specifically during short-circuit conditions detected by the overcurrent protection circuit. The timing generator controls the discharge transistor to operate in pulses rather than continuously, allowing normal power supply function when no fault is present while preventing negative output values when faults occur.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system dynamically adjusts the state of the discharge transistor based on real-time conditions. The timing generator modulates the discharge transistor's activation based on the overcurrent detection signal, transitioning between active and inactive states as needed to maintain positive output values during faults while enabling normal operation during healthy conditions.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12537372B2Semiconductor device
Publication Date: 2026.01.27 KK TOSHIBA
  • US12537372B2 patent drawing
  • US12537372B2 patent drawing
  • US12537372B2 patent drawing

AI summary

According to one embodiment, a semiconductor device includes a first transistor, a first circuit, and a second circuit. A source of the first transistor is coupled to a first terminal. A gate of the first transistor is coupled to a first node. The first circuit includes a first comparator and a current limiting circuit. The second circuit includes a second comparator, a second transistor, a third transistor, and a third circuit. A source of the second transistor is grounded. A drain of the second transistor is coupled to the first node. The third circuit is configured to turn on the second transistor and the third transistor for a first time period based on an output of the second comparator.