Short-Link Interconnect Lanes With Shared CDR Clock Recovery
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Solution Overview
Problem
As semiconductor components become more integrated, higher throughput leads to a higher density of active-circuit blocks and reduced area for heat dissipation, exacerbating interconnect overhead, particularly due to power-hungry clock and data recovery circuitry in longer links.
Innovation Solution
The interconnect scheme employs short die-to-die, die-to-optical-electrical-module, and die-to-memory connections using extra short or ultra short reach links, omitting clock and data recovery circuitry in favor of phase adjustment and clock multiplier circuitries, which act as slaves to a single clock and data recovery circuitry in one lane, reducing channel loss and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock and data recovery circuitry is included in each lane for data transfer across the interconnect, then data integrity and clock synchronization are maintained, but power consumption and circuit area increase significantly
Solution Approach 1:
The patent merges the clock and data recovery functionality from multiple lanes into a single dedicated CDR circuit. Instead of having independent CDR circuits in each lane, one CDR circuit serves multiple lanes, reducing the total power consumption and circuit area while maintaining data integrity through shared clock recovery capabilities
Solution Approach 2:
The single clock and data recovery circuit is designed to serve multiple lanes universally, making it a multi-functional component that can handle data recovery across different lanes. This universal CDR circuit replaces multiple specialized CDR circuits, achieving both power reduction and functional coverage
2Productivity
If higher throughput is achieved through increased component integration, then data transfer capacity improves, but heat dissipation area decreases and interconnect overhead increases
Solution Approach 1:
The patent extracts the clock and data recovery circuitry from the high-density interconnect lanes and places it in a separate, dedicated location. This extraction removes the power-hungry CDR functionality from the crowded interconnect area, reducing local heat generation while maintaining the high throughput capability through efficient data transfer paths
3Use of energy by moving object
If clock and data recovery circuitry is omitted from lanes to reduce power consumption, then power efficiency improves, but clock synchronization and data recovery capability may be compromised
Solution Approach 1:
The patent introduces a dedicated clock and data recovery circuit as an intermediary component that centralizes the clock synchronization function. This intermediary CDR circuit acts as a single point of truth for clock recovery, providing synchronized clocks to multiple lanes without requiring individual CDR circuits in each lane, thus maintaining reliability while reducing power consumption
Data Source
AI summary
Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.