Image Sensor Readout Circuit With Short Ramps for Low-Noise ADC
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Solution Overview
Problem
Modern high-pixel count image sensors face challenges in achieving high frame rate, low read noise, and high dynamic range while minimizing power consumption, leading to shorter battery lifetimes and thermal heating, which affects sensor performance.
Innovation Solution
The implementation of a correlated multiple sampling architecture in integrated-circuit image sensors using short and fast ramps, which involves performing multiple ADC conversions in both the reset and signal conversion phases, averaging output results to reduce thermal noise, and incorporating a programmable gain amplifier to enhance noise reduction and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If higher power is provided to reduce read noise or increase dynamic range, then image quality is improved, but power consumption increases leading to shorter battery lifetimes and thermal heating
Solution Approach 1:
The patent segments the ADC conversion process into multiple independent conversions instead of using a single high-power conversion. By performing multiple lower-power ADC conversions and averaging the results, the system achieves reduced read noise equivalent to higher power consumption while actually consuming less power overall.
Solution Approach 2:
The patent implements periodic action by performing multiple ADC conversions at different time points during the reset and signal conversion phases. These periodic sampling operations are averaged to reduce thermal noise, achieving the noise reduction effect of high power consumption through repeated low-power measurements rather than continuous high-power operation.
2Measurement precision
If higher power is provided to reduce read noise or increase dynamic range, then image quality is improved, but thermal heating increases affecting sensor performance
Solution Approach 1:
The patent divides the conversion task into multiple segments (multiple ADC conversions) performed sequentially rather than using a single high-power conversion. This segmentation distributes the thermal load over time, preventing concentrated heat generation while achieving the same noise reduction effect through averaging of multiple measurements.
Solution Approach 2:
By performing ADC conversions periodically at different phases (reset phase and signal conversion phase) and averaging the results, the system reduces thermal noise without requiring sustained high power that would cause thermal heating. The periodic nature of the conversions allows thermal dissipation between measurements.
3Measurement precision
If multiple ADC conversions are performed to reduce thermal noise, then read noise is reduced, but conversion time increases reducing frame rate
Solution Approach 1:
The patent performs preliminary ADC conversions during the reset phase before the actual signal conversion. By completing some conversions in advance during the reset phase and using those results in the averaging process, the system reduces the time penalty of multiple conversions while maintaining the noise reduction benefit.
Solution Approach 2:
The patent performs a limited number of ADC conversions (not an excessive number) - specifically multiple conversions during reset phase and additional conversions during signal phase. This partial action approach achieves sufficient noise reduction through averaging without the time penalty of performing an excessive number of conversions, optimizing the trade-off between noise reduction and frame rate.
4Measurement precision
If voltage ramp is extended to cover full readout range, then dynamic range is maintained, but conversion time increases
Solution Approach 1:
The patent performs preliminary ADC conversions during the reset phase that cover the full readout range, establishing the dynamic range coverage in advance. This preliminary action ensures that the full dynamic range is captured without requiring extended ramp times during the critical signal conversion phase, thereby maintaining dynamic range while reducing overall conversion time.
Data Source
AI summary
A readout circuit includes a ramp generator for generating a plurality of first short ramps having a first level in a reset conversion phase and a plurality of second short ramps having a second level greater than the first level and a full-scale ramp having a third level greater than the second level in a signal conversion phase, a comparator for comparing a first analog signal with each one of the first short ramps to obtain a plurality of first comparison results in the reset conversion phase, and comparing a second analog signal with each one of the second short ramps and the full-scale ramp in the signal conversion phase to generate a plurality of second comparison results and a third comparison result, and a controller configured to determine an output signal value of the second analog signal according to the plurality of second comparison results and the third result.