Short-Reach Interconnect Lanes With Shared CDR for Lower Power
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Solution Overview
Problem
As semiconductor components become more integrated, higher throughput leads to a higher density of active-circuit blocks and a smaller area for heat dissipation, exacerbating interconnect overhead, particularly due to power-hungry clock and data recovery circuitry in each lane of the interconnect.
Innovation Solution
The interconnect scheme employs short die-to-die, die-to-optical-electrical-module, and die-to-memory connections using extra short reach or ultra short reach links, omitting clock and data recovery circuitry from some lanes and using phase adjustment and clock multiplier circuitries instead, which act as slaves to a CDR circuitry in another lane, reducing channel loss and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full clock and data recovery circuitry is included in each lane of the interconnect, then data transmission reliability is improved, but power consumption and device area increase
Solution Approach 1:
The patent merges the clock and data recovery functionality by having a single CDR circuitry serve multiple lanes through shared resources. The phase adjustment and clock multiplier circuitries are consolidated into common blocks that can be utilized by multiple data lanes, reducing the total power consumption while maintaining reliable data transmission across all lanes.
Solution Approach 2:
The CDR circuitry is designed with universal functionality to serve multiple lanes. The phase adjustment circuitry and clock multiplier are implemented as shared resources that can be dynamically allocated to different lanes as needed, allowing one set of circuitry to perform the function of what would traditionally require separate circuitry in each lane.
2Reliability
If full clock and data recovery circuitry is included in each lane of the interconnect, then data transmission reliability is improved, but device area increases
Solution Approach 1:
The patent merges the clock and data recovery circuitry into shared resources that serve multiple lanes. By consolidating the phase adjustment and clock multiplier functions into common blocks rather than replicating them in each lane, the overall device area is reduced while maintaining the reliability needed for data transmission across all lanes.
Solution Approach 2:
The CDR circuitry is designed as a universal resource that can be shared across multiple lanes. This multi-functional approach allows a single instance of the circuitry to serve the needs of multiple data lanes, significantly reducing the total area required compared to having dedicated circuitry in each lane.
3Productivity
If more active-circuit blocks are integrated to increase throughput, then data transmission speed is improved, but heat dissipation area decreases
Solution Approach 1:
The patent addresses the heat dissipation issue by merging redundant circuitry functions. By consolidating the clock and data recovery operations into shared resources rather than replicating them across multiple lanes, the total number of active circuit blocks is reduced, thereby lowering the overall heat generation while maintaining high throughput capability.
Solution Approach 2:
The patent changes the operational parameters of the interconnect by using phase adjustment and clock multiplication techniques that allow high-speed data transmission without requiring proportionally more active circuit blocks in each lane. This parameter change enables high throughput with reduced circuit density, thereby reducing heat generation.
Data Source
AI summary
Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.