Shortened Address Mode for I3C Serial Bus Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current serial communication protocols, such as I2C and I3C, consume excessive power due to longer IO times, which is a combination of processing and communication time, especially in mobile devices with multiple sensors, necessitating techniques to reduce power consumption.
Innovation Solution
Implementing a shortened address mode in the slave address and register address fields of I3C frames, where the number of address bits is calculated based on the quantity of slaves or registers, allowing for reduced field lengths, thereby minimizing the IO time and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If standard address fields (7-bit slave address, 8-bit register address) are used in I3C communication, then all slaves and registers can be addressed, but the IO time increases leading to higher power consumption
Solution Approach 1:
The patent applies dynamics by making the address field length variable rather than fixed. The master device dynamically determines the number of address bits needed based on the actual quantity of slaves or registers, and adjusts the address field length accordingly. This dynamic adaptation allows the system to use shorter address fields when fewer devices are present, reducing IO time and power consumption while maintaining the ability to address all necessary devices.
Solution Approach 2:
The patent changes the parameter of address field length from a fixed value (7 bits for slave address, 8 bits for register address) to a variable value based on the actual number of slaves or registers. By calculating the minimum bits required (e.g., 1 bit for 1 slave, 2 bits for 2-4 slaves, 3 bits for 5-8 slaves, 4 bits for 9-16 slaves), the system optimizes the address field length to match the actual addressing needs, thereby reducing unnecessary transmission time and energy consumption.
2Loss of time
If shorter address fields are used to reduce IO time, then power consumption decreases, but the ability to address multiple slaves or registers is limited
Solution Approach 1:
The system dynamically adapts the address field length to match the actual number of slaves or registers being addressed. The master device calculates the required bits based on the quantity of devices (e.g., 1 bit suffices for 1 slave, 4 bits for 9-16 slaves) and configures the address fields accordingly. This dynamic approach ensures that the addressing capability matches the actual system configuration, avoiding both over-provisioning (which wastes time) and under-provisioning (which limits capability).
Solution Approach 2:
The patent changes the address field length parameter based on the actual system configuration. Instead of using fixed 7-bit or 8-bit fields, the system calculates and applies the minimum necessary bits (1-4 bits for slave addresses, 1-5 bits for register addresses) based on the quantity of devices. This parameter adaptation maintains full addressing capability for the actual number of devices while minimizing the address field length to reduce IO time.
3Productivity
If fixed-length address fields are used in communication frames, then protocol implementation is simpler, but communication efficiency decreases due to longer transmission time
Solution Approach 1:
The patent introduces dynamic address field length adjustment to improve communication efficiency. The master device calculates the optimal address field length based on the number of slaves or registers, and both master and slave devices dynamically adapt to this variable length. While this adds some complexity to the protocol implementation, the benefit of significantly reduced IO time and improved communication efficiency justifies the additional complexity, especially in systems with fewer devices where the address field can be much shorter than the traditional fixed length.
Data Source
AI summary
Systems, methods, and apparatus for data communication are provided. A device operating as a bus master may be detect one or more slaves on a serial bus supporting a shortened address mode for receiving a waveform having at least one of a shortened slave address or a shortened register address. The bus master may then calculate a number of slave address bits needed to address the one or more slaves in a binary form based on a quantity of the one or more slaves and generate shortened slave addresses for the one or more slaves, respectively. A length of each shortened slave address is the number of slave address bits. The bus master may then assign a generated shortened slave address to each of the one or more slaves and send the waveform to a slave via the serial bus using an assigned shortened slave address.