Shortened Read Attempts for Flash Memory Latency
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Solution Overview
Problem
Flash memory technologies face challenges in achieving fast read speeds due to increasing complexity and latency in multi-level cell architectures, particularly in NAND arrays, which affect data transfer rates and memory density.
Innovation Solution
A method involving shortened read attempts with error correction to provide estimates of data and redundant information, allowing for faster data access while maintaining accuracy by comparing signatures and correcting errors, thereby reducing read latency and increasing overall performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell (MLC) techniques are implemented to increase storage capacity, then memory density is improved, but read latency increases
Solution Approach 1:
The patent performs a shortened read attempt that reads only a portion of the expected data duration, obtaining an early estimate before the full read operation would complete. This partial action allows the system to potentially terminate the read early if the estimate is sufficient, thereby reducing read latency while maintaining the ability to achieve full read accuracy when needed.
Solution Approach 2:
The patent uses the estimate obtained from the shortened read attempt as feedback to determine whether to continue with a full read operation. By comparing the estimate quality against a threshold or using it to guide subsequent read operations, the system dynamically adjusts the read duration based on actual data conditions, optimizing the balance between speed and accuracy.
2Speed
If shortened read attempts are performed to reduce read latency, then read speed is improved, but data accuracy deteriorates
Solution Approach 1:
The patent performs a preliminary shortened read attempt before the full read operation to obtain an early estimate of the data. This preliminary action provides a quick approximation that can be used to determine whether the full read is necessary, allowing the system to achieve fast reads when possible while maintaining accuracy when needed.
Solution Approach 2:
The estimate from the shortened read attempt serves as feedback to control whether to proceed with a full read operation. The system uses this feedback mechanism to dynamically adjust the read operation duration, ensuring data accuracy is maintained when the estimate indicates insufficient information while enabling fast reads when the estimate is sufficient.
3Measurement precision
If error correction is performed to maintain data correctness, then data accuracy is improved, but processing complexity increases
Solution Approach 1:
The patent extracts only the necessary portion of data for the shortened read attempt, obtaining an estimate without performing the complete read operation. By taking out only what is needed for the quick assessment and using that to potentially avoid the full read and subsequent error correction, the system reduces processing complexity while maintaining data correctness when required.
Solution Approach 2:
The patent performs a partial read operation (shortened attempt) instead of the full read operation. This partial action obtains sufficient information for error correction decisions in many cases, reducing the overall processing complexity by avoiding unnecessary full reads and their associated error correction requirements.
Data Source
AI summary
A device, a computer readable medium and a method that may include performing a shortened read attempt of multiple data memory cells that store data to provide an estimate of the data; wherein the shortened read attempt has a duration that is shorter than a duration of a full read attempt; performing a shortened read attempt of redundant memory cells that store redundant information to provide an estimate of the redundant information; wherein the estimate of the redundant information is indicative of an expected number of data memory cells that store a certain logic value; determining, based on the estimate of the data, an estimated number of data memory cells that store the certain logic value; comparing the expected number to the estimated number; and providing the estimate of the data as a read result if the expected number and the estimated number equal each other.