Shrinkable Layer Planarization for Semiconductor Dielectric Dishing
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Solution Overview
Problem
Chemical mechanical polishing (CMP) processes in the semiconductor industry often result in dishing of dielectric layers, which complicates achieving a flat surface necessary for subsequent metal interconnect structures.
Innovation Solution
A shrinkable layer is formed over the dielectric layer with dishing, and a treatment process is applied to flatten the shrinkable layer's top surface based on its topography, allowing the dielectric layer to be planarized and exposed, thereby achieving a flat surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is used to planarize the dielectric layer, then the surface can be made flat, but dishing occurs on the dielectric layer surface
Solution Approach 1:
A shrinkable layer is formed over the dielectric layer before final planarization. This preliminary action creates a compensating structure that will later be shrunk to counteract the dishing, allowing the CMP process to proceed without creating permanent surface deformations.
Solution Approach 2:
The shrinkable layer undergoes a parameter change through thermal or chemical treatment that causes it to shrink. This parameter change (from relaxed state to shrunk state) creates the necessary counteracting force to flatten the dished dielectric layer surface, transforming the surface topology from concave to flat.
2Manufacturing precision
If a shrinkable layer is formed and treated to flatten the surface, then the dielectric layer can be planarized, but additional process steps are required
Solution Approach 1:
The formation of the shrinkable layer is merged with the existing CMP process flow. The shrinkable layer serves dual purposes: it protects the dielectric layer during CMP and provides the mechanism for post-CMP planarization, combining multiple functions into a single integrated approach.
Solution Approach 2:
The shrinkable layer acts as an intermediary between the dished dielectric layer and the final flat surface requirement. It mediates the planarization process by providing a controllable shrinking mechanism that can be activated after CMP to achieve the desired surface flatness without directly modifying the dielectric layer structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively planarizes the dielectric layer by flattening the shrinkable layer, ensuring a smooth surface for subsequent processes, such as metal interconnect formation, by filling and removing the shrinkable layer as needed.
Implementation Method 1
A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface
Data Source
AI summary
A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface.