Shuffler Circuitry for Programmable Test Compactor Diagnosis
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Solution Overview
Problem
Test response compaction in semiconductor device testing can make faults indistinguishable during diagnosis, leading to more suspects and increased work for failure analysis, which is problematic with advanced manufacturing technologies that require higher compression and more expensive failure analysis.
Innovation Solution
The implementation of a circuit with shuffler circuitry that delays output signals from scan chains based on a control signal, inserted between scan chains and a test response compactor, to reduce fault equivalency and improve diagnosis resolution, along with masking circuitry to block unwanted signals and control signal generation/multiplexing circuitry to form the control signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If test response compaction is applied to reduce data volume, then test data volume is reduced, but fault distinguishability deteriorates leading to more suspects
Solution Approach 1:
The shuffler circuitry performs preliminary reordering of test response bits from scan chains before they enter the compactor. By shuffling the bit positions based on control signals, the system prepares the data in a rearranged sequence that prevents fault equivalency during subsequent compaction, thereby maintaining diagnosis resolution while achieving data compression.
Solution Approach 2:
The shuffler circuitry acts as an intermediary component between the scan chains and the test response compactor. This intermediate shuffling stage modifies the direct mapping relationship between scan chain outputs and compactor inputs, preventing direct fault equivalency and enabling better fault distinction after compaction.
2Quantity of substance
If compression ratio is increased to handle larger circuits, then more data can be compressed, but diagnosis resolution deteriorates with more suspects
Solution Approach 1:
Before high-ratio compaction is applied, the shuffler circuitry preemptively rearranges the test response bits to break potential equivalency patterns. This preliminary shuffling ensures that even with aggressive compression ratios, the compacted results maintain sufficient information for accurate fault diagnosis.
Solution Approach 2:
The system dynamically changes the parameter of bit ordering through the shuffler circuitry controlled by control signals. By varying the shuffling pattern based on control signals derived from test patterns or previous responses, the system adapts the data arrangement to maintain diagnosis resolution across different compression scenarios.
3Device complexity
If no shuffling is applied to maintain simple compaction, then device complexity is low, but fault equivalency increases reducing diagnosis quality
Solution Approach 1:
The compaction system is segmented into distinct functional modules: scan chains, shuffler circuitry with state elements, control signal generation circuitry, and test response compactor. This segmentation allows the shuffling function to be added as a separate, manageable component rather than integrating complexity into the core compaction logic.
Solution Approach 2:
The shuffler circuitry serves as an intermediary layer that adds minimal complexity between the scan chains and compactor. By using simple state elements and control signal logic, the system achieves fault distinction enhancement without requiring complex modifications to the compaction algorithm itself.
Data Source
AI summary
A circuit comprises: scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses; a decompressor configured to decompress compressed test patterns into the test patterns; a test response compactor configured to compact the test responses; and shuffler circuitry inserted between outputs of the scan chains and inputs of the test response compactor, the shuffler circuitry comprising state elements configured to delay output signals from some of the scan chains for one or more clock cycles based on a control signal, the control signal varying with the test patterns.