Variable Resistance Memory Shunt Gate Vertical Transistor
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Solution Overview
Problem
Next-generation memory devices, such as PCRAMs, ReRAMs, and MRAMs face challenges with access devices having low threshold voltage and large area occupancy, leading to word line bouncing due to resistance differences when diodes are arranged over word lines.
Innovation Solution
A variable resistance memory device utilizing vertical transistors with a surround gate structure and a shunt gate disposed between adjacent transistors to reduce gate resistance and area, improving word line resistance and capacitance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are used as access devices, then threshold voltage is low, but area occupancy is large
Solution Approach 1:
The patent transitions from planar transistors to vertical transistors, changing the spatial dimension from 2D to 3D. The vertical transistor structure with channel extending in the vertical direction reduces the footprint area while maintaining the gate control functionality, thus reducing area occupancy while preserving low threshold voltage characteristics.
Solution Approach 2:
The gate structure surrounds the channel pillar in a nested configuration, with the gate wrapping around the vertical channel. This nested arrangement allows the gate to control the channel from multiple directions (surround gate effect), improving control efficiency and reducing the required gate area compared to planar structures.
2Area of moving object
If diodes are arranged over word line, then area is reduced, but word line bouncing occurs due to resistance difference
Solution Approach 1:
The shunt gate is electrically connected to the gate of each vertical transistor, creating an equipotential region across the word line. This connection equalizes the potential distribution and reduces resistance differences along the word line, thereby minimizing word line bouncing effects while maintaining compact area.
3Reliability
If gate area is increased, then word line resistance is improved, but device area increases
Solution Approach 1:
The gate structure extends in the vertical dimension rather than solely in the planar direction. The surround gate configuration allows the gate to achieve larger effective area for better word line resistance without increasing the footprint area, as the gate area is expanded through the vertical channel height.
Data Source
AI summary
A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor.