Shuttle Mask Dummy Patterns for IC Design Isolation
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Solution Overview
Problem
The challenge is to effectively prevent IC design owners from accessing each other's IC designs on a multi-project wafer, while also improving pattern density uniformity in shuttle mask design.
Innovation Solution
The method involves adding dummy insertion patterns in separate chip regions, which are duplicates of the main patterns, and optionally adding dummy lines to ensure the BEOL structure layers match or differ, thereby separating and concealing the IC designs from each other.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple IC designs are combined on the same shuttle mask to save R&D cost, then the cost efficiency is improved, but the risk of IC design leakage between different IC design owners increases
Solution Approach 1:
The patent introduces dummy patterns as intermediary elements between different IC designs on the same shuttle mask. These dummy patterns act as visual separators and obfuscators that prevent direct observation of adjacent IC designs while maintaining the overall mask structure for cost-efficient multi-project wafer fabrication.
2Loss of information
If dummy patterns are added to separate and conceal IC designs, then the security against design leakage is improved, but the pattern density uniformity and manufacturing complexity increase
Solution Approach 1:
The patent applies parameter changes by adjusting the density, size, and distribution of dummy patterns to achieve visual separation of IC designs while maintaining overall pattern density uniformity. The dummy patterns are strategically designed with specific parameters (density, spacing, size) that balance security requirements with manufacturing considerations.
Data Source
AI summary
A design method of a shuttle mask including the following steps is provided. A first integrated circuit (IC) design is provided in a first chip region, and a second IC design is provided in a second chip region. The first IC design includes first main patterns. The second IC design includes second main patterns. First dummy insertion patterns are added in the first chip region, and second dummy insertion patterns are added in the second chip region. The first main patterns and the first dummy insertion patterns are separated from each other. The first dummy insertion patterns are patterns formed by duplicating at least one of the first main patterns. The second main patterns and the second dummy insertion patterns are separated from each other. The second dummy insertion patterns are patterns formed by duplicating at least one of the second main patterns.