SiCON Contact Etch Stop Layer for Parasitic Capacitance Reduction
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Solution Overview
Problem
Existing field-effect transistor manufacturing processes face challenges in achieving efficient and cost-effective scaling down while maintaining complexity and production efficiency, as current methods are not entirely satisfactory in all respects.
Innovation Solution
The method involves forming a field effect transistor using a fin structure with a dummy gate electrode, a contact etch stop layer (CESL) of SiCON, and a protection layer, where the CESL is used to reduce parasitic capacitance and protect the source and drain regions from oxidation, and the dummy gate is replaced with a real gate electrode, utilizing advanced patterning and deposition techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down geometry size is implemented to increase functional density, then production efficiency and cost-effectiveness are improved, but processing complexity increases
Solution Approach 1:
A contact etch stop layer (CESL) is formed over the source and drain regions before subsequent processing steps. This preliminary action prevents oxidation of the source and drain regions during later manufacturing steps, eliminating the need for complex protective measures and simplifying the overall processing sequence while enabling continued scaling
2Area of stationary object
If scaling down geometry size is implemented to increase functional density, then chip area utilization is improved, but manufacturing complexity increases
Solution Approach 1:
The CESL is deposited in advance over the source and drain regions, creating a protective barrier before any oxidation-prone processes. This preliminary protective action allows for aggressive scaling and high-density integration without complicating the manufacturing process, as the same CESL layer protects all scaled-down devices uniformly across the chip
3Reliability
If parasitic capacitance is reduced to improve device performance, then transistor efficiency is improved, but additional processing steps are required
Solution Approach 1:
The contact etch stop layer serves multiple functions simultaneously: it acts as an etch stop during contact hole formation, provides oxidation protection for source and drain regions, and reduces parasitic capacitance between the gate and source/drain regions. By combining these functions into a single layer, the patent achieves improved device performance without adding processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by reducing parasitic capacitance and improving the manufacturing process efficiency, allowing for more complex and efficient integration of transistors in semiconductor ICs.
Implementation Method 1
the CESL is used to reduce parasitic capacitance
Implementation Method 2
protect the source and drain regions from oxidation
Data Source
AI summary
Field effect transistor and methods of forming the same are disclosed. The field effect transistor includes a gate electrode, a contact etch stop layer (CESL), an inter layer dielectric (ILD) and a protection layer. The CESL includes SiCON and is disposed on a sidewall of the gate electrode. The IDL is laterally adjacent to the gate electrode. The protection layer covers the CESL and is disposed between the CESL and the ILD.