Si-Ge Epitaxial Source Drain Stress for PMOS Mobility
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Solution Overview
Problem
Current semiconductor device manufacturing processes for MOS transistors face challenges in simplifying the application of stress to channel regions to enhance carrier mobility, leading to complex processes and instability in manufacturing.
Innovation Solution
A method involving the formation of gate electrodes, side wall spacers, and epitaxial growth of Si—Ge-containing crystals in recesses, along with the deposition of stress-inducing insulating films, to apply compressive and tensile stress to PMOS and NMOS regions respectively, while simplifying the process by removing the sacrificial film during recess formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stress films are formed above NMOS and PMOS regions to improve carrier mobility, then mobility is enhanced, but the manufacturing process becomes complex and unstable
Solution Approach 1:
The patent extracts the stress application function from complex separate stress films and integrates it into the source/drain region structures themselves. By forming Si-C mixed crystal in NMOS source/drain regions and Si-Ge mixed crystal in PMOS source/drain regions, the stress is applied directly through the crystal structure without requiring additional stress film deposition processes, thereby simplifying manufacturing while maintaining mobility enhancement
Solution Approach 2:
The source/drain regions serve multiple functions: they provide electrical connection, define transistor boundaries, and simultaneously apply stress to the channel through their crystal structure. This multi-functionality eliminates the need for separate stress application structures, reducing process complexity while achieving the desired mobility improvement
2Reliability
If separate stress application methods are used for NMOS and PMOS, then mobility is improved, but the number of manufacturing steps increases
Solution Approach 1:
The patent merges the stress application process with the source/drain formation process. By using ion implantation to introduce carbon into NMOS source/drain regions and germanium into PMOS source/drain regions during the same manufacturing sequence, both transistor types receive their respective stress treatments in an integrated process flow, improving manufacturing efficiency while maintaining mobility enhancement for both device types
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the manufacturing process and improves carrier mobility by applying stress closer to the channel, enhancing the performance of complementary type semiconductor devices.
Implementation Method 1
When the source/drain regions of a PMOS transistor are made of silicon-germanium (Si—Ge) mixed crystal having a lattice constant larger than the Si substrate, compressive stress is applied to the Si crystal in the channel region and hole mobility becomes high.
Implementation Method 2
by forming the contact etch stopper film with a tensile stress film above the NMOS region and forming the contact etch stopper film with a compressive stress film above the PMOS region
Implementation Method 3
When the source/drain regions of an NMOS transistor are made of silicon-carbon (Si—C) mixed crystal (C-doped Si) having a lattice constant smaller than the Si substrate, tensile stress is applied to the Si crystal in the channel region and electron mobility becomes high.
Data Source
AI summary
A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers.