Si-Substrate-Free Interposer Stacked Vias Signal Integrity

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Solution Overview

Problem

Conventional integrated circuit packages using silicon substrates face signal degradation and complexity issues due to the presence of silicon substrates, which hinder the performance of circuits and connections.

Innovation Solution

The development of silicon-substrate-free (Si-less) packages using dielectric layers with through-dielectric vias and stacked vias to replace traditional through-silicon vias, allowing for direct bonding of device dies and interconnects without silicon substrates, enabling efficient signal communication and thermal dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional through-silicon vias are used in silicon substrates, then interconnection is achieved, but signal degradation occurs and chip area is occupied

Engineering Contradiction:

Improvesignal integrityVSAvoidchip area occupation

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts and removes the silicon substrate from the interposer structure, replacing it with a carrier board that has through-dielectric vias. This extraction eliminates the signal degradation issues associated with silicon substrates while reducing the area occupied by the interposer, as the carrier board can be optimized independently of the device dies.

Inventive Principle:

Principle #2Taking out (Extraction)

2Strength

If silicon substrates are used for interposer, then structural support is provided, but signal degradation and complexity increase

Engineering Contradiction:

Improvestructural supportVSAvoidpackage complexity

Core Design Contradiction:

StrengthVSDevice complexity

Solution Approach 1:

The patent introduces a carrier board as an intermediary element that replaces the silicon substrate. The carrier board serves as a mediator that provides the necessary structural support and mechanical strength while allowing for simplified interconnection structures through through-dielectric vias, thereby reducing overall package complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If through-silicon vias are formed, then electrical interconnection is achieved, but manufacturing complexity and signal loss increase

Engineering Contradiction:

Improveelectrical interconnectionVSAvoidmanufacturing complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent inverts the conventional approach by forming through-dielectric vias in the carrier board before bonding the device dies, rather than forming through-silicon vias after substrate preparation. This inversion allows for simpler manufacturing processes, better alignment control, and reduced signal loss since the vias are formed in a controlled dielectric environment rather than through silicon material.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS11527465B2Packages with Si-substrate-free interposer and method forming same

Publication Date: 2022.12.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked vias in the plurality of dielectric layers with the stacked vias forming a continuous electrical connection penetrating through the plurality of dielectric layers, forming a dielectric layer over the stacked vias and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding.