Molecular Level SiO2 Interface Layer Formation for CMOS Devices
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Solution Overview
Problem
In semiconductor technology, particularly for CMOS devices at the 45 nm node and below, there are challenges in forming a stable and ultra-thin SiO2 interface layer for metal gate/high-K dielectric structures due to thermal instability and interface state issues, which affect the equivalent oxide thickness (EOT) and device performance.
Innovation Solution
A method involving cleansing with an HF/isopropyl alcohol/water solution, followed by rapid thermal annealing in N2 to form a molecular level SiO2 interface layer, combined with high-K gate dielectric film deposition and metal nitride gate formation, utilizing techniques like physical vapor deposition and reactive magnetic sputtering, while controlling oxygen invasion to maintain a small EOT.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a natural oxide layer is formed on the silicon surface, then the SiO2 interface layer is created, but the thickness becomes too large (5-6 Å) and continues to grow during device manufacture
Solution Approach 1:
The patent applies preliminary action by performing rapid thermal annealing (RTA) in a nitrogen atmosphere immediately after silicon surface preparation and before high-K dielectric deposition. This RTA treatment (500-600°C for 30-90 seconds) creates an ultra-thin SiO2 interface layer (0.5-0.7 nm) in advance, preventing subsequent oxide growth during device manufacturing processes. The nitrogen atmosphere prevents contamination while the controlled thermal treatment forms the desired thin oxide layer before further processing occurs.
2Manufacturing precision
If the SiO2 interface layer thickness is reduced to decrease EOT, then device performance improves, but the layer becomes too thin and difficult to control
Solution Approach 1:
The patent applies parameter changes by precisely controlling RTA processing parameters (temperature: 500-600°C, time: 30-90 seconds, atmosphere: nitrogen) to form an ultra-thin SiO2 interface layer with thickness of 0.5-0.7 nm. This controlled thermal treatment creates a stable, uniform thin oxide layer that achieves low EOT (2-5 nm) while maintaining interface quality and preventing excessive growth during subsequent device fabrication steps.
Solution Approach 2:
The patent uses an inert nitrogen atmosphere during the rapid thermal annealing process to prevent contamination of the silicon surface and control oxide formation. The nitrogen environment prevents unwanted chemical reactions and contamination while allowing controlled SiO2 interface layer formation through thermal treatment, ensuring reliability of the ultra-thin layer.
3Reliability
If metal gate/high-K dielectric structure is used to reduce gate tunneling current, then device reliability improves, but interface state problems and thermal stability issues arise
Solution Approach 1:
The patent introduces an ultra-thin SiO2 interface layer (0.5-0.7 nm) as an intermediary between the silicon substrate and the high-K dielectric layer. This thin oxide layer serves as a buffer that improves interface quality, reduces interface states, and enhances thermal stability of the metal gate/high-K dielectric structure. The interface layer acts as a mediator that prevents direct interaction between silicon and high-K material, reducing interface-related problems while maintaining the benefits of reduced gate tunneling current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces EOT, improves gate leakage current, and enhances interface states, resulting in a high-quality high-K gate dielectric film suitable for high-performance nanometer-level CMOS devices by suppressing natural oxide growth and contamination.
Implementation Method 1
cleansing a wafer and immersing the wafer in HF/isopropyl alcohol/water solution at room temperature
Implementation Method 2
forming the molecular level SiO2 interface layer by performing rapid thermal annealing on the wafer in N2 for 30-90 seconds at 500-600° C.
Implementation Method 3
forming the molecular level SiO2 interface layer by performing rapid thermal annealing on the wafer in N2
Implementation Method 4
forming a high-K gate dielectric film by forming the high-K gate dielectric film by physical vapor deposition
Implementation Method 5
depositing a metal nitride gate on the high-K dielectric film by reactive magnetic sputtering
Implementation Method 6
reactive magnetic sputtering
Implementation Method 7
performing rapid thermal annealing, whereby the rapid thermal annealing is conducted at 500-600° C. for 30-90 seconds in the Gate-Last process or at 800-1000° C. for 20-40 seconds in the Gate-First process
Implementation Method 8
performing rapid thermal annealing, whereby the rapid thermal annealing is conducted
Data Source
AI summary
The present disclosure provides a method for forming and controlling a molecular level SiO2 interface layer, mainly comprising: cleansing before growing the SiO2 interface layer, growing the molecular level ultra-thin SiO2 interface layer; and controlling reaction between high-K gate dielectric and the SiO2 interface layer to further reduce the SiO2 interface layer. The present disclosure can strictly prevent invasion of oxygen during process integration. The present disclosure can obtain a good-quality high-K dielectric film having a small EOT. The manufacturing process is simple and easy to integrate. It is also compatible with planar CMOS process, and can satisfy requirement of high-performance nanometer level CMOS metal gate/high-K device of 45 nm node and below.