Si/SiC Vertical MOSFET Structure for Gate Oxide Stability
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Solution Overview
Problem
Conventional power MOSFETs using SiC layers face issues with low channel mobility, increased channel resistance, and gate oxide instability due to carbon at the gate oxide interface, as well as undesirable voltage drops and high leakage currents in SiC/Si heterojunctions, limiting their practicality.
Innovation Solution
A vertical power MOSFET structure is developed with a narrow bandgap Si top layer over a wider bandgap SiC layer, featuring a n-N heterojunction, which includes a bottom SiC or polycrystalline SiC substrate, doped trench gate electrodes, and a dielectric gate oxide, resulting in higher breakdown voltage, lower on-resistance, and improved thermal conductivity, along with a long-channel JFET that shields the gate oxide and reduces leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If SiC layers are used in power MOSFETs, then breakdown voltage and thermal conductivity are improved, but channel mobility decreases and gate oxide stability deteriorates
Solution Approach 1:
The device is segmented into two distinct regions: a SiC drift region for high voltage blocking and a Si channel region for low-resistance conduction. This spatial segmentation allows each material to perform its optimal function without the drawbacks of using SiC throughout the entire device structure.
Solution Approach 2:
The Si channel layer acts as an intermediary between the SiC drift region and the gate oxide, preventing direct contact between carbon-containing SiC and the gate oxide interface, thereby eliminating carbon contamination while still benefiting from SiC's high voltage blocking capability.
2Loss of energy
If SiC/Si heterojunction is used, then specific on-resistance is reduced, but voltage drop and leakage current increase
Solution Approach 1:
The device structure implements local quality by using SiC specifically in the drift region where high voltage blocking is needed, and Si in the channel region where low resistance and low leakage are critical. This localized material selection optimizes performance in each region without introducing harmful effects elsewhere.
3Temperature
If SiC drift layer is used, then thermal conductivity is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: growing the SiC drift region first, then epitaxially growing the Si channel layer on top. This segmentation allows each layer to be optimized independently using appropriate growth conditions and doping strategies, simplifying the overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves lower specific on-resistance, higher reliability, and ease of gate drive, with most voltage drops occurring across the SiC JFET and drift region, minimizing the impact on the gate oxide and reducing leakage current, while allowing for high-density trench gates and efficient electron current flow.
Implementation Method 1
The MOSFET cell with one or more trench gates utilizes a narrow bandgap Si top layer over a wider bandgap SiC layer, where the heterojunction is n-N rather than P—N
Implementation Method 2
The gate electrodes are surrounded by a dielectric material, such as silicon dioxide (SiO2), formed completely within the Si epitaxial layer
Implementation Method 3
a long-channel JFET that shields the gate oxide and reduces leakage current
Implementation Method 4
N+ source regions, a P-type P-well (body), and P+ contact regions (connected to the source metal) are all formed in the silicon
Data Source
AI summary
A vertical MOSFET has an N-type SiC drift layer connected to a drain electrode. An overlying Si layer creates an n-N heterojunction at the top of the SiC drift layer. A P-well layer and N+ source regions are formed in the Si layer. Trenched gates are formed in the Si layer that invert the P-well to create a conductive path between the Si source regions and the SiC drift region. JFET channel regions and gate regions are formed in the SiC layer for improving reliability of the MOSFET under reverse voltage conditions and under short circuit conditions. The SiC drift layer results in a higher breakdown voltage, lower on-resistance, and improved thermal conductivity, and the upper Si layer retains its higher channel mobility and stability and high gate drive efficiency.