Si and SiGe Fin Integration via Epitaxial Growth and Annealing

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Solution Overview

Problem

The integration of silicon (Si) and silicon germanium (SiGe) fins in finFET devices faces challenges such as defectivity issues and loss of epitaxial growth selectivity, particularly for high-Ge-concentration SiGe layers, which affect the formation of p-channel FET regions in CMOS devices.

Innovation Solution

A method involving the formation of Si fins on a buried oxide layer, followed by epitaxial growth of a SiGe layer and a thermal annealing process to drive Ge into the Si fins, ensuring the formation of SiGe fins with controlled dimensions, thereby integrating Si and SiGe fins of the same dimensions across regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If advanced patterning techniques are used to pattern the SiGe fin, then the fin dimensions can be controlled, but defectivity issues and loss of epitaxial growth selectivity occur

Engineering Contradiction:

Improvefin dimensionsVSAvoiddefectivity

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by forming the oxide mask layer before epitaxial growth of the SiGe layer. This mask layer is deposited and patterned in advance to define the regions where SiGe will grow, ensuring that the epitaxial growth occurs only in desired locations while maintaining selectivity and reducing defects. The preliminary masking prevents unwanted SiGe formation that would cause defectivity issues.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements local quality by creating spatially varying fin thicknesses across different regions of the substrate. The oxide mask is selectively removed or patterned in specific regions, causing SiGe epitaxial growth to occur only in certain areas, resulting in local variations in fin dimensions and composition tailored to specific device requirements while maintaining overall process reliability.

Inventive Principle:

Principle #3Local quality

2Reliability

If high-Ge-concentration SiGe layers are used, then the p-channel FET performance is improved, but epitaxial growth selectivity is lost

Engineering Contradiction:

Improvep-channel FET performanceVSAvoidepitaxial growth selectivity

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent uses an oxide mask layer as an intermediary between the substrate and the high-Ge-concentration SiGe layer. This intermediary layer controls where the SiGe epitaxial growth occurs by being selectively removed or thinned in specific regions. The oxide mask enables the use of high-Ge-concentration SiGe for improved p-channel FET performance while maintaining epitaxial growth selectivity through the mediating role of the mask layer.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Adaptability or versatility

If Si and SiGe fins are integrated on the same wafer, then CMOS device functionality is achieved, but process complexity increases

Engineering Contradiction:

ImproveCMOS device functionalityVSAvoidprocess complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the formation of Si fins and SiGe fins into a single integrated process flow on the same wafer. Both fin types are formed using the same basic epitaxial growth process, with the oxide mask enabling selective SiGe growth in p-channel regions while Si fins form in n-channel regions. This merging approach achieves CMOS device functionality while reducing overall process complexity compared to separate processing steps.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the integration of Si and SiGe fins, reducing defectivity and improving epitaxial growth selectivity, allowing for the formation of CMOS devices with improved fin dimensions and device performance.

Implementation Method 1

depositing an oxide mask over the first region

Methodology Applied

Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

epitaxially growing an SiGe layer on the at least one of the at least two Si fins in the second region

Methodology Applied

Scientific EffectEpitaxy: Epitaxy

Implementation Method 3

performing a thermal annealing process to drive Ge from the SiGe layer into the at least one of the at least two Si fins in the second region

Methodology Applied

Scientific EffectDiffusion: Diffusion

Data Source

PatentUS9276013B1Integrated formation of Si and SiGe fins

Publication Date: 2016.03.01 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A method of fabricating silicon (Si) and silicon germanium (SiGe) fins is described. The method includes forming at least two Si fins on a buried oxide (BOX) layer disposed on a substrate, at least one Si fin being formed in a first region and at least one Si fin being formed in a second region, the at least one Si fin in the second region being thinner than the at least one Si fin in the first region. The method also includes depositing an oxide mask over the first region, epitaxially growing an SiGe layer on the at least one Si fin in the second region, and performing a thermal annealing process to drive Ge from the SiGe layer into the at least one Si fin in the second region to form at least one SiGe fin in the second region.