Sibling Net Delay Calculation Sharing in EDA
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Solution Overview
Problem
Existing electronic design automation (EDA) tools face significant performance overhead and increased runtime during Static Timing Analysis (STA), particularly in hierarchical designs, due to the high cost of delay calculation, especially when dealing with multiple corners and modes, which is exacerbated by the need for repeated delay calculations across identical or similar components.
Innovation Solution
The method identifies sibling nets with the same input slew rate in electronic designs and shares a stored delay calculation among them, reducing the need for redundant calculations by storing and reusing delay calculations across multiple instances of hierarchical blocks, thereby optimizing the delay calculation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delay calculation is performed for each sibling net individually, then calculation accuracy is maintained, but runtime increases significantly
Solution Approach 1:
The patent merges the delay calculation process for multiple sibling nets by identifying nets with identical input slew rates and reusing the same delay calculation model and results across these nets. This combining approach maintains accuracy for nets that share characteristics while eliminating redundant calculations, directly resolving the contradiction between maintaining precision and reducing runtime.
Solution Approach 2:
The patent creates a universal delay calculation model that can be applied across multiple sibling nets with the same input slew rate. This single model serves multiple functions by calculating delays for any net within the sibling group, eliminating the need for separate calculations and achieving both accuracy and efficiency.
2Loss of time
If delay calculation is shared across sibling nets, then runtime is reduced, but calculation accuracy may be compromised
Solution Approach 1:
The patent applies local quality by making the delay calculation sharing conditional rather than universal. It identifies specific sibling nets with matching input slew rates and applies shared calculations only to those nets, while maintaining individual calculations for nets with different characteristics. This ensures accuracy is preserved where needed while achieving runtime reduction where applicable.
Solution Approach 2:
The patent uses parameter changes by comparing the input slew rate parameter across sibling nets to determine whether to share delay calculations. When the slew rate parameter matches, the nets are grouped together for shared calculation; when it differs, individual calculations are performed, thus maintaining accuracy while enabling optimization.
3Reliability
If all MMMC corners are analyzed, then timing verification completeness is improved, but computational cost increases
Solution Approach 1:
The patent performs preliminary action by identifying and grouping sibling nets with identical input slew rates before executing the full MMMC analysis. This pre-grouping enables the subsequent multi-corner analysis to reuse delay calculations across corners for sibling nets, reducing the overall computational cost while maintaining complete timing verification across all MMMC conditions.
Data Source
AI summary
The present disclosure relates to a computer-implemented method for use with an electronic design. Embodiments include identifying, using one or more processors, a plurality of sibling nets associated with the electronic design and determining if the plurality of sibling nets have a same input slew rate. If the plurality of sibling nets do not have a same input slew rate, embodiments also include determining a delay calculation (DC) for each of the plurality of sibling nets. If the plurality of sibling nets do have a same input slew rate, embodiments further include sharing a stored DC with the plurality of sibling nets.