Sibling Wire Routing for Signal Delay Reduction
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Solution Overview
Problem
As semiconductor process technology advances to 7 nm and below, the increase in process rule complexity and narrower metal wires lead to higher electrical resistance and signal delay, which slows down circuits, and traditional workarounds like widening wires or using via pillars become impractical due to design rule restrictions and inefficiencies.
Innovation Solution
Implementing sibling wire routing and via placement, where multiple parallel wires and vias are used to reduce resistance and electromigration issues, allowing for efficient routing and placement without compromising complex design rules, using design tools to automatically detect critical nets and introduce sibling elements dynamically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wire width is reduced to match advanced process technology (7 nm and below), then manufacturing precision is improved, but electrical resistance increases and signal delay increases
Solution Approach 1:
The patent divides a single wire into multiple parallel sibling wires (e.g., two or more wires running side by side). Each wire maintains the narrow width required for 7 nm process precision, but the combined parallel structure provides multiple conduction paths, effectively reducing total resistance and signal delay while adhering to the manufacturing precision requirements of advanced processes.
2Reliability
If wire width is increased to reduce resistance, then electrical resistance decreases, but design rule complexity is violated and manufacturing becomes impractical
Solution Approach 1:
Instead of widening a single wire (which would violate design rules at 7 nm), the patent segments the conduction function across multiple narrow parallel wires. Each individual wire remains within the strict width specifications required by advanced manufacturing processes, while the collective arrangement achieves the desired electrical conductivity without violating any design rules.
3Adaptability or versatility
If via pillars are used to route signals, then routing flexibility is improved, but device complexity increases and placement efficiency decreases
Solution Approach 1:
The patent merges the routing function into the metal layer itself by placing sibling wires directly in the metal layer without requiring via pillars for routing. This consolidation eliminates the need for complex via pillar structures and multiple routing steps, reducing device complexity while maintaining routing flexibility through the parallel wire arrangement.
Data Source
AI summary
A placed netlist is routed. A circuit is obtained that implements the placed netlist. A net in the circuit is identified to be enhanced. Space adjacent to a wire associated with the net that would accommodate a parallel wire is reserved.