SiC Semiconductor Alignment Mark Compensation for Epitaxial Deviation
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Solution Overview
Problem
In semiconductor device manufacturing, positional deviations of alignment marks due to off-angle epitaxial growth can lead to lithography deviations, resulting in increased contact resistance and variation in forward voltage and ON resistance, posing challenges in maintaining consistent device performance.
Innovation Solution
A semiconductor device structure and manufacturing method that includes a planar substrate with a silicon carbide single crystal, a drift layer, a base region, and upper and base contact regions, where the alignment mark positional deviation is accounted for by setting the width of gaps and openings to accommodate the expected deviation, ensuring accurate ion implantation and reducing overlapping errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If alignment marks are read using conventional photolithography processes, then the position information is obtained for subsequent processes, but positional deviations occur due to epitaxial growth causing the alignment mark pattern to collapse in the off-angle direction
Solution Approach 1:
The patent applies preliminary action by forming a compensation pattern during the photolithography process that anticipates and compensates for the alignment mark position deviation caused by epitaxial growth. The compensation pattern is designed with predetermined offset dimensions that pre-correct for the expected collapse direction and magnitude, ensuring accurate final positioning despite the off-angle growth effects
Solution Approach 2:
The patent implements beforehand cushioning by designing the compensation pattern with extended dimensions in the collapse direction that absorb and accommodate the alignment mark position deviation. This cushioning design ensures that even when the alignment mark collapses during epitaxial growth, the compensation pattern maintains sufficient overlap to achieve accurate positioning
2Measurement precision
If multiple alignment marks are formed to prevent reading errors, then reading accuracy is improved, but the number of photolithography processes increases thus increasing manufacturing burden
Solution Approach 1:
The patent merges the alignment mark function with the compensation pattern into a single integrated structure. By combining these functions, the system achieves both accurate alignment mark reading and deviation compensation without requiring separate formation processes, thereby reducing the total number of photolithography steps while maintaining high reading accuracy
Solution Approach 2:
The compensation pattern serves multiple functions: it acts as an alignment reference, provides deviation compensation, and ensures accurate positioning. This multi-functionality eliminates the need for separate alignment marks and compensation structures, reducing process complexity while maintaining measurement precision
3Ease of manufacture
If ion implantation regions overlap with base contact regions, then manufacturing is simplified, but conductivity types cancel each other out increasing contact resistance
Solution Approach 1:
The patent applies preliminary action by designing the compensation pattern with predetermined offset dimensions that pre-prevent the overlap between ion implantation regions and base contact regions. The compensation pattern is configured with sufficient margin in the collapse direction to ensure that even when alignment marks deviate during epitaxial growth, the regions remain separated, thus preventing conductivity cancellation and maintaining low contact resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes and reduces variation in forward voltage and ON resistance, preventing defects and maintaining consistent device performance even with alignment mark reading errors, while also simplifying the photolithography process by allowing the reuse of initial alignment marks.
Implementation Method 1
When epitaxial growth is performed on the base semiconductor substrate (or on an epitaxial layer formed on the base SiC substrate), the shape of the alignment mark that is initially dug into the top surface of the SiC semiconductor substrate (or on the epitaxial layer formed on the SiC semiconductor substrate) is also transferred to the top surface of the epitaxially grown film deposited on the semiconductor substrate
Implementation Method 2
consecutively fabricating this type of source region and base contact region with photolithography processes, if the n-type impurity ion implantation region that will serve as the source region and the p-type impurity ion implantation region that will serve as the base contact region overlap each other
Data Source
AI summary
This semiconductor device includes: an n-type SiC drift layer; a p-type base region; an n-type source region selectively embedded in the top part of the base region; p-type base contact regions selectively embedded in the top part of the base region so as to form a first gap with the source region along the <11-20> direction; a gate electrode provided via a gate insulating film; and an n-type drain region. The top surface of the drain region has an off-angle relative to the <11-20> direction towards the <0001> direction, and an alignment mark for positioning is formed on the top surface. The drift layer and the base region are epitaxially grown films, and a width wg of the first gap is set in accordance with a positional deviation width of the alignment mark caused by the off-angle and epitaxial growth.