Silicon Carbide Alignment Using Asymmetric Recess Geometry
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Solution Overview
Problem
Existing methods for manufacturing silicon carbide semiconductor devices do not achieve sufficient alignment precision, particularly when using silicon carbide substrates with angled main surfaces, leading to asymmetric recess formation and reduced alignment accuracy.
Innovation Solution
A method involving the formation of a first silicon carbide layer with a recess and a second silicon carbide layer, where the ratio of the recess depth to the second layer's thickness is greater than 0.2, allowing for improved alignment precision by using the image of a second recess formed on the second layer's surface for alignment purposes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a trench is used as an alignment mark in a silicon carbide substrate with off direction, then alignment precision between substrate and mask is improved, but the recess formed is asymmetric leading to reduced alignment accuracy
Solution Approach 1:
The patent applies asymmetry by intentionally designing the alignment mark with a specific asymmetric geometry that compensates for the asymmetric deformation caused by the off-cut substrate orientation. The alignment mark has a first side length different from a second side length, creating a controlled asymmetry that counteracts the substrate-induced asymmetry, thereby restoring alignment accuracy.
Solution Approach 2:
The patent changes the geometric parameters of the alignment mark by defining specific ratios between the depth of the first recess and the thickness of the second silicon carbide layer (ratio > 0.2), and by specifying different side lengths for the alignment mark. These parameter changes ensure that the alignment mark maintains its functionality despite the asymmetric deformation from the off-cut substrate.
2Measurement precision
If the depth of the first recess is increased to improve alignment precision, then alignment precision is improved, but the ratio constraint (depth/thickness > 0.2) must be maintained
Solution Approach 1:
The patent establishes a specific parameter relationship (depth of first recess divided by thickness of second silicon carbide layer greater than 0.2) that optimizes alignment precision while maintaining manufacturability. This parameter constraint provides a clear design guideline that balances alignment performance with process feasibility.
Data Source
AI summary
A method for manufacturing a silicon carbide semiconductor device includes the following steps. There is prepared a first silicon carbide layer having a first main surface and a second main surface. A first recess including a side portion and a bottom portion is formed in the first main surface of the first silicon carbide layer. A second silicon carbide layer is formed in contact with the first main surface, the side portion, and the bottom portion. An image of a second recess formed at a position facing the first recess of the fourth main surface is obtained. Alignment is performed based on the image of the second recess. The first main surface corresponds to a plane angled off relative to a {0001} plane. A ratio obtained by dividing a depth of the first recess by a thickness of the second silicon carbide layer is more than 0.2.