SiC Barrier Layer for FinFET Impurity Diffusion Control
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Solution Overview
Problem
In semiconductor manufacturing, the diffusion of impurities from the well region into the channel region of Fin FET devices during thermal operations leads to performance degradation, random dopant fluctuation, and threshold voltage mismatch, which challenges the achievement of high device performance and reliability.
Innovation Solution
A silicon carbide (SiC) or silicon compound barrier layer is epitaxially grown over the substrate to suppress impurity diffusion, and co-implantation dopants are used to control dopant profiles, thereby reducing back-diffusion and enhancing dopant confinement between the channel and well regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If thermal operations are performed during manufacturing, then doping and annealing processes can be completed, but impurity diffusion from well region into channel region occurs causing performance degradation
Solution Approach 1:
A barrier layer comprising silicon carbide (SiC) or a silicon compound is introduced between the well region and channel region. This intermediary layer suppresses impurity diffusion during thermal operations while allowing the manufacturing process to proceed, thereby resolving the contradiction between completing doping/annealing processes and preventing performance degradation.
2Ease of manufacture
If dopant diffusion is allowed during manufacturing, then doping process is simplified, but random dopant fluctuation and threshold voltage mismatch occur
Solution Approach 1:
The barrier layer acts as a mediator that confines dopants within the well region during implantation and annealing processes. This enables simplified doping procedures while preventing random dopant fluctuation and threshold voltage mismatch by maintaining precise dopant profile control through the barrier layer's suppression of unintended diffusion.
3Manufacturing precision
If higher temperature annealing is performed, then dopant activation is improved, but impurity back-diffusion into channel region increases
Solution Approach 1:
The silicon carbide or silicon compound barrier layer serves as a thermal-stable intermediary that permits higher temperature annealing for improved dopant activation while simultaneously blocking impurity back-diffusion into the channel region, thus resolving the contradiction between activation efficiency and contamination prevention.
4Reliability
If barrier layer is added to suppress impurity diffusion, then device performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The barrier layer is formed by epitaxial growth of silicon carbide or silicon compound, utilizing existing semiconductor manufacturing techniques. By changing the material parameter (introducing SiC or silicon compound layer) rather than fundamentally altering the process flow, device performance is improved while minimizing increases in manufacturing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves short channel control, carrier mobility, and reduces random dopant fluctuation, resulting in better device performance and yield by maintaining an abrupt dopant profile and minimizing channel defect formation.
Implementation Method 1
A silicon carbide (SiC) or silicon compound barrier layer is epitaxially grown over the substrate to suppress impurity diffusion
Implementation Method 2
A silicon carbide (SiC) or silicon compound barrier layer is epitaxially grown over the substrate
Data Source
AI summary
In a method for manufacturing a semiconductor device, a doped layer is formed in a substrate. A barrier layer that is in contact with the doped layer is formed. A semiconductor layer is formed over the substrate and the barrier layer. A fin structure is formed by patterning the semiconductor layer, the barrier layer, and the doped layer such that the fin structure includes a channel region including the semiconductor layer and a well region including the doped layer. An isolation insulating layer is formed such that a first portion of the fin structure protrudes from the isolation insulating layer and a second portion of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over the fin structure and the isolation insulating layer.