SiC BJT Defect Termination Layer and Carrier Lifetime Control
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Solution Overview
Problem
Silicon carbide (SiC) bipolar junction transistors (BJTs) face degradation due to basal plane dislocations and stacking faults, which affect their electrical parameters and stability, particularly in high-power devices, as these defects can form resistive barriers and reduce current gain.
Innovation Solution
A defect termination layer (DTL) is introduced between the substrate and the collector region, and a zone with a shorter minority charge carrier lifetime is created in the collector region to terminate dislocations and prevent the growth of stacking faults, thereby enhancing the stability of the SiC BJT.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard SiC BJT structure is used with off-axis substrate, then the device can be manufactured with acceptable initial performance, but basal plane dislocations propagate into the epitaxial layers causing degradation of electrical parameters during operation
Solution Approach 1:
The collector region is divided into two distinct zones: an upper collector region with standard properties and a lower collector region with reduced minority carrier lifetime. This segmentation allows the lower zone to act as a barrier against dislocation propagation while maintaining the electrical performance of the upper zone, thereby improving long-term stability without excessive complexity
Solution Approach 2:
A defect termination layer is introduced as an intermediary structure between the off-axis substrate and the collector region. This layer specifically terminates basal plane dislocations before they can propagate into the active epitaxial layers, preventing degradation of electrical parameters while allowing the use of cost-effective off-axis substrates
2Strength
If the collector region is made thicker to improve voltage blocking capability, then the breakdown voltage increases, but the propagation distance for dislocations and stacking faults increases, worsening device stability
Solution Approach 1:
Different zones within the collector region are assigned different properties: the lower zone has reduced minority carrier lifetime to terminate dislocations, while the upper zone maintains standard properties for voltage blocking. This local differentiation allows the device to achieve both high breakdown voltage and improved stability against dislocation propagation
Solution Approach 2:
The solution addresses the thickness-stability trade-off by introducing a new dimension: minority carrier lifetime distribution. Instead of simply reducing collector thickness, the invention creates a vertical gradient in carrier lifetime, with the lower region having shorter lifetime to block dislocation propagation while the overall collector thickness can be maintained for voltage blocking requirements
3Reliability
If minority carrier lifetime in the collector region is reduced to prevent stacking fault growth, then device stability improves, but switching losses may increase due to slower carrier removal
Solution Approach 1:
The minority carrier lifetime is reduced only in the lower collector region where dislocation termination is needed, while the upper collector region maintains standard carrier lifetime properties. This localized approach improves stability against bipolar degradation in the critical lower region while minimizing the impact on switching performance in the upper region
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the risk of bipolar degradation and improves the long-term stability of SiC BJTs by preventing the propagation of basal plane dislocations and stacking faults, leading to increased device performance and reliability.
Implementation Method 1
a defect termination layer (DTL) for terminating dislocations originating from the substrate is arranged between the substrate and the collector region
Implementation Method 2
The collector region includes a zone in which the lifetime of the minority charge carriers is shorter than in the base region
Data Source
AI summary
A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT (100) are provided. The SiC BJT comprises an emitter region (150), a base region (140) and a collector region (120). The collector region is arranged on a substrate (110) having an off-axis orientation of about 8 degrees or lower. A defect termination layer (DTL, 130) for terminating dislocations originating from the substrate is arranged between the substrate and the collector region. The collector region includes a zone (125) in which the life time of the minority charge carriers is shorter than in the base region. The present invention is advantageous in terms of improved stability of the SiC BJTs.