SiC Trench Body Diode Screening for Stacking Fault Yield
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Solution Overview
Problem
Conventional methods for detecting stacking faults in silicon carbide semiconductor devices result in poor yield due to the conversion of basal plane dislocations into stacking faults, leading to increased non-conforming semiconductor chips and high ON voltage degradation.
Innovation Solution
A silicon carbide semiconductor device with a trench gate structure is designed to operate at elevated temperatures, where the body diode conduction is used to grow stacking faults, and the device is inspected to ensure the stacking fault area is within a predetermined range relative to the active region, allowing for conforming products to be identified and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional detection methods (laser irradiation or body diode conduction) are used to detect stacking faults, then stacking faults can be identified, but basal plane dislocations convert into stacking faults during the process, increasing the number of non-conforming chips and reducing yield
Solution Approach 1:
The invention changes the operating temperature parameter to at least 100°C, which fundamentally alters the behavior of stacking faults. At this elevated temperature, stacking faults do not cause increase in ON voltage, allowing defective chips to be distinguished from conforming chips based on their temperature-dependent electrical characteristics rather than physical defect presence
Solution Approach 2:
The invention converts the previously harmful effect of stacking faults (causing ON voltage increase at room temperature) into a beneficial detection mechanism. By operating at elevated temperature, the stacking faults' adverse effects are suppressed, and the body diode conduction at this temperature becomes a reliable indicator for identifying conforming chips without causing dislocation-to-fault conversion
2Loss of information
If stacking faults are grown by laser irradiation or body diode conduction for detection, then stacking fault positions can be identified, but the process increases ON voltage and creates more non-conforming chips
Solution Approach 1:
The invention changes the temperature parameter to at least 100°C, which suppresses the adverse effects of stacking faults on ON voltage. This parameter change allows stacking faults to be present without degrading device reliability, as the elevated operating temperature prevents the typical ON voltage increase associated with stacking faults
3Reliability
If strict quality control is applied to exclude chips with stacking faults, then device reliability is maintained, but yield decreases due to high exclusion rate
Solution Approach 1:
The invention changes the operating temperature parameter to at least 100°C, which fundamentally alters the relationship between stacking faults and device performance. At this temperature, stacking faults do not cause ON voltage increase, allowing chips with stacking faults to be classified as conforming and included in the product, thereby improving yield while maintaining reliability
Solution Approach 2:
The invention converts the presence of stacking faults from a reliability issue into a yield improvement opportunity. By operating at elevated temperature where stacking faults do not adversely affect performance, the invention allows previously non-conforming chips to be sold as conforming products
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces the adverse effects of stacking faults by maintaining a high breakdown voltage and operating temperature, enabling the identification of conforming products and enhancing yield, even when stacking faults are present, by setting the operating-environment temperature to at least 100 degrees C.
Implementation Method 1
a device element structure including a pn junction between the second semiconductor region and the first semiconductor region that forms a body diode
Data Source
AI summary
A silicon carbide semiconductor device being capable of operating at least 100 degree C., includes a semiconductor substrate having an active region, the semiconductor substrate having first and second surfaces opposite to each other, a first semiconductor region of an n type, provided in the semiconductor substrate, a second semiconductor region of a p type, provided in the active region, between the first surface of the semiconductor substrate and the first semiconductor region, and a device element structure including a pn junction between the second and first semiconductor regions that forms a body diode through which a current flows when the semiconductor device is turned on. A stacking fault area that is a sum of areas that contain stacking faults within an entire active region of the first surface of the semiconductor substrate in the first surface is set to be greater, the higher a breakdown voltage is set.