SiC Trench Structure With 3C/4H Boundary Control for Low Leakage
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Solution Overview
Problem
The existing SiC semiconductor devices face challenges in maintaining design flexibility due to unclear boundaries between 3C-SiC and 4H-SiC regions, leading to increased contact resistance and leak current, particularly in trench-type devices where impurity concentration control in the depth direction is difficult.
Innovation Solution
The SiC semiconductor device incorporates a multilayer structure with a first silicon carbide layer of 4H structure and a second silicon carbide layer of 3C structure, where the second layer is formed by film deposition, clearly defining the boundary between the two, allowing for a deeper gate electrode placement and reducing leak current without additional margin, and is manufactured using a method that includes epitaxial growth and ion implantation followed by activation annealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation is used to form 3C-SiC region, then the region can be created, but the boundary between 3C-SiC and 4H-SiC regions becomes unclear
Solution Approach 1:
The patent changes the manufacturing method parameter from ion implantation to film deposition (CVD or sputtering) for forming the 3C-SiC layer. This parameter change enables clear boundary formation between 3C-SiC and 4H-SiC regions while maintaining manufacturing feasibility, resolving the contradiction between boundary clarity and ease of manufacture.
2Reliability
If gate electrode is placed deeper to reduce leak current, then leak current decreases, but device design flexibility decreases due to unclear boundaries
Solution Approach 1:
By changing the formation method to film deposition, the patent achieves clear boundary definition between 3C-SiC and 4H-SiC regions. This enables the gate electrode to be placed deeper for leak current suppression without sacrificing design flexibility, as the clear boundary provides precise spatial reference for electrode positioning.
3Manufacturing precision
If ion implantation is used to control impurity concentration in depth direction, then impurity distribution can be achieved, but control precision is difficult
Solution Approach 1:
The patent changes from ion implantation to film deposition methods (CVD or sputtering) for forming the 3C-SiC layer. This parameter change simplifies the control of impurity concentration in the depth direction while achieving precise manufacturing, reducing process control complexity.
4Manufacturing precision
If film deposition is used to form 3C-SiC layer, then boundary clarity improves and manufacturing cost decreases, but additional silicide layers may be needed
Solution Approach 1:
The patent changes the formation method to film deposition, achieving clear boundary definition and reduced manufacturing cost. The potential issue of additional silicide layers is addressed by selecting appropriate deposition parameters and materials to achieve the desired electrical properties without excessive layer complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device design flexibility by clearly defining the 3C-SiC and 4H-SiC regions, suppresses leak current, and reduces manufacturing costs by using a less expensive system for forming the 3C-SiC layer, while maintaining low contact resistance without the need for additional silicide layers.
Implementation Method 1
a second silicon carbide layer containing silicon carbide with a 3C structure and stacked on the top face of the first silicon carbide layer
Implementation Method 2
forming a first conductivity type main region having a multilayer structure of a source extension region and a source contact region
Implementation Method 3
manufactured using a method that includes epitaxial growth and ion implantation followed by activation annealing
Data Source
AI summary
Provided is a SiC semiconductor device that suppresses the decrease in the device design flexibility. The SiC semiconductor device includes a first SiC layer 14 containing SiC with a 4H structure, a second SiC layer 15 containing SiC with a 3C structure and stacked on the top face of the first SiC layer, a first conductivity type drift layer 2 provided in the first SiC layer, second conductivity type base regions 5a, 5b provided in the first SiC layer, first conductivity type main regions 6a, 6b including source extension regions 61a, 61b provided in the first SiC layer and source contact regions 62a, 62b provided in the second SiC layer, a gate insulating film 7b provided in a trench 7a penetrating the main region and the base region, a gate electrode 7c embedded in the trench, and a main electrode (11, 12) provided in contact with the source contact region.