SiC Substrate Buffer Layer Design for Stacking Fault Suppression
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Solution Overview
Problem
Silicon carbide semiconductor substrates suffer from crystal defects and dislocations, particularly basal plane dislocations, which lead to increased ON voltage and bipolar degradation due to excessive current flow, causing triangular and bar stacking faults during semiconductor device operation.
Innovation Solution
A silicon carbide semiconductor substrate design featuring a buffer layer with a high impurity concentration of at least 1.0×10^18/cm^3 and a voltage blocking layer with a lower impurity concentration, strategically positioned to suppress the growth of stacking faults by preventing excessive hole injection and covering the buffer layer's end to prevent diffusion and scratches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick buffer layer is formed by epitaxial growth to prevent excessive hole injection, then bipolar degradation is suppressed, but manufacturing complexity and cost increase
Solution Approach 1:
The buffer layer is divided into multiple layers with different impurity concentrations: a first buffer layer with higher impurity concentration (1×10^18 to 1×10^19/cm³) and a second buffer layer with lower impurity concentration (1×10^17 to 1×10^18/cm³). This segmentation allows each layer to perform specific functions - the first layer suppresses hole injection while the second layer reduces resistance, achieving bipolar degradation suppression without requiring excessive thickness
Solution Approach 2:
Different regions of the buffer layer are assigned different impurity concentrations tailored to local requirements. The first buffer layer near the substrate has higher impurity concentration to prevent hole injection at the critical substrate interface, while the second buffer layer has lower concentration to minimize resistance in the current conduction path
2Reliability
If a highly doped layer is formed to capture electrons and suppress stacking faults, then triangular and bar stacking faults are reduced, but impurity diffusion and contamination risk increase
Solution Approach 1:
The impurity concentration parameter is precisely controlled within specific ranges (1×10^18 to 1×10^19/cm³ for the first buffer layer, 1×10^17 to 1×10^18/cm³ for the second). This optimized parameter selection provides sufficient doping to suppress stacking faults while avoiding excessive doping that would cause impurity diffusion and contamination during subsequent manufacturing processes
Solution Approach 2:
The buffer layers with optimized impurity concentrations are formed in advance during epitaxial growth before subsequent device fabrication steps. This preliminary action establishes a stable foundation that suppresses stacking fault formation during bipolar operation while the controlled impurity levels prevent contamination during later manufacturing processes
3Reliability
If the buffer layer thickness is increased to suppress hole injection, then electron-hole recombination is reduced, but manufacturing time and cost increase
Solution Approach 1:
The buffer layer is segmented into two thinner layers instead of one thick layer. The first buffer layer (5-20 μm) provides hole injection suppression, while the second buffer layer (2-10 μm) provides low-resistance current conduction. This segmentation achieves the same electron-hole recombination suppression effect as a thick single layer but with reduced total thickness and shorter epitaxial growth time
Solution Approach 2:
Each buffer layer segment is assigned a specific impurity concentration optimized for its local function. The first layer's higher concentration efficiently suppresses hole injection with thinner thickness, while the second layer's lower concentration minimizes resistance. This local optimization reduces the total buffer layer thickness required compared to a uniform thick buffer layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively suppresses the occurrence of triangular and bar stacking faults, preventing their growth towards the substrate center and reducing the risk of contamination and defect formation during manufacturing, thereby enhancing the reliability and performance of silicon carbide semiconductor devices.
Implementation Method 1
a buffer layer of the first conductivity type provided on a front surface of the central part of the silicon carbide substrate, the buffer layer being introduced with a first impurity that determines a conductivity type of the silicon carbide substrate and a second impurity different from the first impurity
Implementation Method 2
an epitaxial layer of the first conductivity type provided on a front surface of the peripheral part of the silicon carbide substrate
Data Source
AI summary
A silicon carbide semiconductor substrate, including a silicon carbide substrate of a first conductivity type, a buffer layer of the first conductivity type and an epitaxial layer of the first conductivity type. The silicon carbide substrate has a central part and a peripheral part surrounding the central part, and is doped with a first impurity that determines the first conductivity type. The buffer layer is provided on a front surface of the central part of the silicon carbide substrate, and is doped with the first impurity, of which a concentration is at least 1.0×1018/cm3, and a second impurity different from the first impurity. The epitaxial layer is provided on a front surface of the peripheral part of the silicon carbide substrate, and is doped with the first impurity, of which a concentration is lower than the concentration of the first impurity in the buffer layer.