SiC-Buffered GaN Substrate for High Voltage Reliability
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Solution Overview
Problem
Existing methods for manufacturing compound semiconductor substrates using GaN layers face challenges in achieving high vertical withstand voltage while minimizing current collapse, as doping GaN with carbon increases defects and traps electrons, leading to degraded performance.
Innovation Solution
A method involving the formation of a SiC layer on a Si substrate, followed by alternating AlN layers at specific temperature ranges, and subsequent growth of nitride semiconductor layers to improve crystal quality and reduce defects, thereby enhancing vertical withstand voltage and reducing current collapse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If GaN layer is doped with carbon to improve vertical withstand voltage, then insulation breakdown resistance increases, but defects increase and electron trapping sites increase leading to current collapse
Solution Approach 1:
The patent introduces a SiC layer as an intermediary between the Si substrate and the GaN layer. This SiC buffer layer mediates the lattice mismatch and thermal expansion differences, enabling high-quality GaN growth without carbon doping. The SiC layer has a lattice constant intermediate between Si and GaN, providing a gradual transition that reduces dislocation density and eliminates the need for harmful carbon doping to achieve high withstand voltage.
Solution Approach 2:
The patent changes the substrate material parameter from pure Si to SiC-buffered Si substrate. This parameter change fundamentally alters the growth conditions for GaN, enabling the formation of high-quality crystalline structures without requiring carbon doping. The SiC buffer layer modifies the thermal and structural parameters of the substrate system, allowing GaN to grow with fewer defects and without the need for compensatory doping.
2Ease of manufacture
If Si substrate is used for GaN device, then manufacturing cost is reduced, but warpage and cracks occur due to lattice constant and thermal expansion differences
Solution Approach 1:
The SiC layer serves as a mediator between the Si substrate and the GaN layer. It compensates for the lattice mismatch and thermal expansion coefficient differences between Si and GaN, preventing warpage and cracks while maintaining the cost advantage of using Si substrates. The SiC buffer layer absorbs the mechanical stress caused by the material property differences.
Solution Approach 2:
The patent applies local quality improvement by introducing a SiC buffer layer only at the critical interface region between Si substrate and GaN layer. This localized intervention addresses the specific problem of lattice mismatch and thermal stress at the substrate interface without requiring changes to the entire substrate or device structure, thus maintaining cost effectiveness while improving manufacturing precision.
3Reliability
If AlN buffer layer is formed at high temperature to improve crystal quality, then defect density decreases, but manufacturing process complexity increases
Solution Approach 1:
The patent changes the temperature parameter for AlN buffer layer formation to an optimized range of 700-1000°C. This parameter optimization achieves high crystal quality and low defect density without requiring excessively complex manufacturing processes. The specific temperature range balances crystal growth quality with process feasibility and equipment requirements.
Solution Approach 2:
The patent segments the buffer layer structure into multiple functional layers: SiC buffer layer for lattice matching, followed by AlN buffer layer for defect reduction. This segmentation allows each layer to perform its specific function optimally, achieving high crystal quality through a systematic multi-layer approach rather than relying on a single complex process step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in a compound semiconductor substrate with improved crystalline quality, reduced electron trapping sites, and increased vertical withstand voltage, effectively addressing the current collapse issue while maintaining high insulation breakdown voltage.
Implementation Method 1
a step to form a SiC layer on a Si substrate
Implementation Method 2
a step to form a first AlN layer having a thickness of 12 nanometers or more and 100 nanometers or less on the SiC layer at 700 degrees Celsius or more and 1000 degrees Celsius or less
Implementation Method 3
a step to form a first AlN layer having a thickness of 12 nanometers or more and 100 nanometers or less on the SiC layer at 700 degrees Celsius or more and 1000 degrees Celsius or less
Implementation Method 4
a step to form a first nitride semiconductor layer containing Al on the second AlN layer, a step to form a GaN layer on the first nitride semiconductor layer
Data Source
AI summary
A method for manufacturing a compound semiconductor substrate comprises: a step to form an SiC (silicon carbide) layer on a Si (silicon) substrate, a step to form a LT (Low Temperature)-AlN (aluminum nitride) layer with a thickness of 12 nanometers or more and 100 nanometers or less on the SiC layer at 700 degrees Celsius or more and 1000 degrees Celsius or less, a step to form a HT (High Temperature)-AlN layer on the LT-AlN layer at a temperature higher than the temperature at which the LT-AlN layer was formed, a step to form an Al (aluminum) nitride semiconductor layer on the HT-AlN layer, a step to form a GaN (gallium nitride) layer on the Al nitride semiconductor layer, and a step to form an Al nitride semiconductor layer on the GaN layer.