SiC Power Semiconductor Structure for Higher Channel Density
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Solution Overview
Problem
Power semiconductor devices using silicon carbide face challenges in increasing channel density due to negative charges from carbon clusters in the gate insulating layer, leading to higher threshold voltage and channel resistance, which limits high-speed switching operations.
Innovation Solution
A silicon carbide power semiconductor device design with a drift region, well regions, and a channel region, including protruding portions and source regions, along with a gate insulating layer and gate electrode layer, is implemented to enhance channel density and switching performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon carbide is used as the semiconductor layer, then breakdown voltage and heat release characteristics are improved, but channel density is limited due to negative charges from carbon clusters in the gate insulating layer
Solution Approach 1:
The drift region is designed with protruding portions that extend in the vertical dimension beneath the gate electrode layer. This three-dimensional structure increases the effective channel area without expanding the lateral footprint, thereby increasing channel density while preserving the high breakdown voltage characteristics of silicon carbide.
Solution Approach 2:
The drift region is segmented into multiple protruding portions that are spatially separated and extend vertically. This segmentation allows for increased channel formation areas beneath the gate electrode layer, effectively increasing channel density while maintaining the electrical isolation and breakdown characteristics of the silicon carbide material.
2Stability of the object's composition
If carbon clusters form in the gate insulating layer, then silicon carbide stability is maintained, but threshold voltage and channel resistance increase
Solution Approach 1:
By extending the drift region vertically beneath the gate electrode layer, the invention creates additional channel formation areas in the vertical dimension. This compensates for the increased threshold voltage by providing more parallel conduction paths, thereby reducing the overall impact of threshold voltage increase on device performance.
Solution Approach 2:
The invention changes the geometric parameters of the drift region by creating protruding portions with specific dimensions and spacing. This structural parameter change increases the effective channel width and reduces channel resistance, compensating for the harmful effects of carbon cluster formation in the gate insulating layer.
3Ease of manufacture
If source contact structure is disposed between gate electrodes, then electrical connection is achieved, but distance between gate electrodes cannot be decreased
Solution Approach 1:
The drift region protruding portions extend vertically beneath the gate electrode layer, utilizing the vertical dimension to increase channel area. This allows for reduced lateral spacing between gate electrodes since the additional channel area is obtained through vertical extension rather than lateral expansion, thereby enabling smaller gate electrode distances while maintaining electrical connection functionality.
Data Source
AI summary
A power semiconductor device includes a semiconductor layer of SiC, a gate insulating layer, a gate electrode layer, a drift region including at least one protruding portion in the semiconductor layer and having a first conductivity type, a well region including a first well region in the semiconductor layer and in contact with the protruding portion, and a second well region in the semiconductor layer outside the gate electrode layer and connected to the first well region, and having a second conductivity type, a source region including a first source region in the first well region and a second source region in the second well region and connected to the first source region, and having the first conductivity type, and a channel region under the gate electrode layer, in the semiconductor layer between the protruding portion and the first source region, and having the first conductivity type.