SiC Power Transistor Channel Layout With Sacrificial Sidewall Etching
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Solution Overview
Problem
Silicon carbide power transistors face challenges in reducing resistance, particularly due to the high channel resistance, which affects their performance and efficiency.
Innovation Solution
A method is developed to form semiconductor devices by precisely controlling the channel length through a wet etching process, using a sacrificial layer to define the P-type and N-type doped regions, and forming a P-type lightly doped region to clad the heavily doped regions, thereby reducing the resistance and enhancing the device's voltage withstand capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the channel length is reduced to lower channel resistance, then the on-resistance decreases and device efficiency improves, but the breakdown voltage capability deteriorates
Solution Approach 1:
The patent applies local quality by creating different doping concentrations in specific regions: lightly doped regions in the channel area to maintain low resistance, and heavily doped regions at the drain and source areas to ensure high breakdown voltage capability. This spatial variation in doping quality allows simultaneous optimization of both resistance and voltage withstand properties.
Solution Approach 2:
The channel region is segmented into multiple lightly doped regions rather than a uniform structure. This segmentation allows precise control of the electric field distribution, enabling the channel to maintain low resistance while the segmented structure prevents electric field concentration that would compromise breakdown voltage.
2Ease of manufacture
If conventional doping methods are used to form doped regions, then the manufacturing process is simple, but the precision in controlling channel length and doping distribution is insufficient
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary element that enables precise channel length definition. This sacrificial layer serves as a temporary structure that guides the formation of lightly doped regions with exact dimensions, achieving high manufacturing precision while maintaining process simplicity through the intermediary's role as a positioning template.
Solution Approach 2:
The sacrificial layer is formed in advance before the actual doping process. This preliminary action establishes the precise geometric framework for subsequent doping operations, ensuring that the channel length and doping distribution are controlled with high precision before the main manufacturing steps commence.
3Loss of energy
If a single doped region structure is used, then the device structure is simple, but the resistance cannot be effectively reduced without compromising voltage withstand capability
Solution Approach 1:
The device structure incorporates multiple doped regions with locally optimized properties: lightly doped regions where low resistance is critical (channel areas) and heavily doped regions where high voltage withstand is critical (drain and source areas). This local differentiation of doping quality reduces overall resistance while maintaining voltage capability without requiring excessive structural complexity.
Solution Approach 2:
The patent transitions from a single uniform doped region to a multi-dimensional doping architecture with varying concentrations across different spatial zones. This dimensional expansion in doping design allows simultaneous optimization of resistance and voltage properties by exploiting the third dimension of doping concentration variation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the resistance of silicon carbide power transistors by precisely defining the channel length and improving the breakdown voltage, leading to more efficient and reliable semiconductor devices.
Implementation Method 1
A first wet etching process is performed to pattern the sacrificial layer, so that a sidewall of the sacrificial layer is above the substrate inside the P-type heavily doped region
Implementation Method 2
during forming the P-type lightly doped region, a dopant penetrates the first dielectric layer and is implanted into the substrate
Data Source
AI summary
A method of forming a semiconductor device includes forming a P-type heavily doped region in a substrate. A sacrificial layer is formed on the substrate and covers the P-type heavily doped region. The sacrificial layer is patterned, so that sidewalls of the sacrificial layer are above the substrate inside the P-type heavily doped region. An N-type heavily doped region adjacent to the P-type heavily doped region is formed in the substrate by using the sacrificial layer as mask. A wet etching process is performed to retract the sidewalls of the sacrificial layer to the substrate inside the N-type heavily doped region. A P-type lightly doped region is formed in the substrate by using the sacrificial layer as mask. The P-type lightly doped region is adjacent to the N-type heavily doped region, and is in contact with bottoms of the P-type heavily doped region and the N-type heavily doped region.