Silicon Carbide Channel Smoothing via Sacrificial Oxide
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Solution Overview
Problem
Fabricating silicon carbide power devices, such as MOSFETs, is challenging due to difficulties in achieving the required depths and lateral control of p-base and n+ source regions, leading to surface roughness issues that increase on-resistance and reduce reliability.
Innovation Solution
A method involving the formation of an n− silicon carbide layer on a substrate, a p-type well region, a buried p+ region, and an n+ region, with a channel region adjacent to the buried p+ region, where a portion of the n− region is removed using chemical mechanical polishing to reduce surface roughness, and sacrificial oxide layers are used to further smooth the surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation is used to implant p-base and n+ source regions, then dopant depth control is improved, but lateral alignment precision deteriorates due to difficulty in controlling lateral extent and the need for two separate implantation masks
Solution Approach 1:
A sacrificial oxide layer is introduced as an intermediary material between the implantation process and the final device structure. This oxide layer serves as a temporary mask during implantation, allowing for better lateral alignment control, and is subsequently removed to reveal the properly aligned doped regions.
Solution Approach 2:
The oxide layer is formed preliminarily before ion implantation to establish precise lateral boundaries. This preliminary structuring enables accurate alignment of the p-base and n+ source regions during the subsequent implantation process, resolving the lateral alignment precision issue.
2Reliability
If multiple ion implantation and annealing steps are performed, then dopant activation is improved, but surface roughness increases due to step-bunched surfaces across the channel
Solution Approach 1:
The problematic step-bunched surface structure is extracted and removed through selective etching processes. By removing the rough, step-bunched portions of the surface while preserving the underlying doped regions, the patent eliminates the surface roughness issue while maintaining dopant activation.
Solution Approach 2:
The oxide layer is formed preliminarily to protect the surface during implantation and annealing, preventing the formation of severe step bunches. This preliminary protective action reduces surface roughness before the final device structure is completed.
3Ease of manufacture
If conventional diffusion process is used to form p-base and n+ source regions, then manufacturing simplicity is improved, but depth control deteriorates due to small diffusion coefficients in silicon carbide
Solution Approach 1:
The oxide layer acts as an intermediary that enables precise depth control during ion implantation. By controlling the implantation energy and angle through the oxide mask, the patent achieves accurate dopant depth placement in silicon carbide, overcoming the limitations of conventional diffusion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a significant reduction of root mean square surface roughness from 28 Å to less than 1.0 Å, improving the performance and reliability of silicon carbide power devices by smoothing the channel region and reducing on-resistance.
Implementation Method 1
a portion of the n− region is removed from the channel region so that a portion of the n− region remains on the channel region to provide a reduction in a surface roughness of the channel region
Implementation Method 2
sacrificial oxide layers are used to further smooth the surface
Data Source
AI summary
Methods of forming silicon carbide power devices are provided. An n− silicon carbide layer is provided on a silicon carbide substrate. A p-type silicon carbide well region is provided on the n− silicon carbide layer. A buried region of p+ silicon carbide is provided on the p-type silicon carbide well region. An n+ region of silicon carbide is provided on the buried region of p+ silicon carbide. A channel region of the power device is adjacent the buried region of p+ silicon carbide and the n+ region of silicon carbide. An n− region is provided on the channel region and a portion of the n− region is removed from the channel region so that a portion of the n− region remains on the channel region to provide a reduction in a surface roughness of the channel region.