SiC Chip Cleavage Sidewalls to Reduce Dicing Defects
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Solution Overview
Problem
The existing blade dicing process for SiC semiconductor wafers results in crystal defects, chipping, and microcracking on the side surfaces of semiconductor chips, leading to current leakage and reduced reliability due to heat and thermal stress during operation.
Innovation Solution
The process involves forming scribe lines on the SiC semiconductor wafer using a scribing tool and applying an external force along these lines to divide the wafer, exposing the side surfaces in crystal planes (cleavage planes) to preserve the crystal structure, reduce defects, and enhance bending strength and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If blade dicing is used to divide the semiconductor wafer, then the wafer can be divided into chips, but crystal defects and chipping occur on the side surfaces
Solution Approach 1:
The patent replaces the mechanical blade dicing process with a laser-based processing method. The laser beam processes the wafer along predetermined lines to form division lines, eliminating the mechanical contact that causes chipping and crystal defects. This substitution of mechanical system with optical/thermal system resolves the contradiction between productivity and side surface quality.
Solution Approach 2:
The patent changes the processing parameters by using laser energy instead of mechanical force. The laser parameters (power, speed, wavelength) are optimized to create precise division lines without causing damage to the side surfaces. This parameter change enables high-quality side surfaces while maintaining efficient wafer division.
2Productivity
If blade dicing is used to divide the semiconductor wafer, then chips are produced, but microcracking and chipping reduce reliability
Solution Approach 1:
The laser-based division method replaces mechanical blade dicing, eliminating the source of microcracking and chipping. This substitution maintains high chip production rates while significantly improving chip durability by avoiding mechanical stress and contact damage during the division process.
Solution Approach 2:
The patent converts the laser's thermal effect, which could potentially cause damage, into a beneficial tool for creating clean division lines. By carefully controlling laser parameters, the thermal energy is used to precisely separate the wafer without causing microcracks or chipping, thus converting a potential harmful effect into a benefit for reliability.
3Ease of manufacture
If side surfaces are formed orthogonal to the main surface by blade dicing, then division is achieved, but the side surfaces deviate from the cleavage plane causing crystal defects
Solution Approach 1:
The laser processing system replaces mechanical blade dicing, enabling precise control of the division line path. The laser can follow the crystallographic cleavage plane orientation while maintaining the simplicity of the division process. This substitution allows the side surfaces to align with the cleavage plane, preserving crystal structure integrity without complicating the manufacturing process.
Solution Approach 2:
The patent changes the approach by using laser parameters (beam direction, power, speed) to match the crystallographic orientation of the wafer. By adjusting these parameters, the division lines are formed along the cleavage planes, maintaining crystal structure integrity while keeping the process simple and efficient.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces crystal defects and chipping, improving the bending strength and reliability of SiC semiconductor chips by ensuring the side surfaces are formed on cleavage planes, thereby minimizing current leakage and thermal stress issues.
Implementation Method 1
forming scribe lines on the SiC semiconductor wafer using a scribing tool
Implementation Method 2
applying an external force along these lines to divide the wafer, exposing the side surfaces in crystal planes (cleavage planes)
Data Source
AI summary
A SiC semiconductor device including a SiC semiconductor layer composed of SiC single crystal. The SiC semiconductor layer comprising a mounted surface on which an element is mounted, a non-mounted surface opposed to the mounted surface, and a side surface connecting the mounted surface to the non-mounted surface, wherein the side surface is on a cleavage plane of the SiC single crystal.