SiC Complementary JFET Layout for Stable High-Temperature Operation
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Solution Overview
Problem
Current SiC junction field effect transistors face challenges with unstable operation at high temperatures and complex production processes, particularly in forming complementary logic circuits, due to high-density defects at the SiC substrate and gate oxide interface and the intricacy of trench formation and polishing processes.
Innovation Solution
A SiC junction field effect transistor design featuring a SiC substrate with a first conductivity type channel region, a second conductivity type embedded gate region, and source and drain regions, where the n-channel and p-channel JFETs are formed apart and electrically insulated, allowing for stable high-temperature operation and simplified production through ion implantation techniques that minimize channeling phenomena.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a gate oxide film is formed on the SiC substrate to create a MOSFET, then the device can operate at high temperatures, but high-density defects and charges at the interface cause threshold voltage instability and gate oxide degradation
Solution Approach 1:
The patent removes the gate oxide film entirely from the SiC MOSFET structure and replaces it with a metal gate electrode directly contacting the SiC substrate. This extraction of the problematic gate oxide layer eliminates the source of interface defects and charges that cause threshold voltage instability, while the metal gate maintains the necessary electrical control function.
Solution Approach 2:
The patent employs a simple metal layer (such as tungsten or titanium nitride) as the gate electrode instead of a complex gate oxide structure. This metal gate is easier to form, more stable at high temperatures, and eliminates the reliability issues associated with thin oxide films, effectively replacing the fragile oxide-based gate with a robust metal-based gate.
2Reliability
If an intrinsic SiC layer is used to insulate and separate n-channel and p-channel JFETs, then electrical isolation is achieved, but the production process becomes extremely complicated with repeated trench formation, embedding, growing, and polishing
Solution Approach 1:
The patent combines the n-channel and p-channel JFET structures into a single integrated device on the SiC substrate, with both channels sharing common source and drain regions. This merging eliminates the need for complete electrical isolation between the channels, as the shared regions provide natural electrical connection, thereby simplifying the production process by removing multiple trench formation, embedding, and polishing steps.
Solution Approach 2:
The patent segments the gate structures of the n-channel and p-channel JFETs spatially, positioning them in different regions of the substrate, while allowing the source and drain regions to be shared. This segmentation approach maintains electrical isolation where needed (at the gate level) while enabling sharing of common regions, reducing process complexity without compromising device functionality.
3Manufacturing precision
If ion implantation is used to form channel and gate regions, then manufacturing precision can be controlled, but channeling phenomena occur that affect impurity distribution
Solution Approach 1:
The patent modifies the ion implantation parameters by adjusting the acceleration energy, implantation angle, and temperature conditions to suppress channeling phenomena. By changing these parameters, the patent achieves more uniform impurity distribution in the channel and gate regions while maintaining precise control over the doping profiles, thereby resolving the contradiction between manufacturing precision and distribution uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enables stable operation at high temperatures and facilitates easy production of complementary JFETs by controlling threshold voltage through precise impurity density and thickness adjustments, ensuring reliable performance and reduced production complexity.
Implementation Method 1
a second conductivity type embedded gate region formed below the channel region on the principal surface side in the SiC substrate
Implementation Method 2
simplified production through ion implantation techniques that minimize channeling phenomena
Data Source
AI summary
A SiC junction field effect transistor includes a SiC substrate, a first conductivity type channel region formed in the principal surface of the SiC substrate, a second conductivity type embedded gate region formed below the channel region on the principal surface side in the SiC substrate, and first conductivity type source region and drain region formed with the channel region interposed therebetween in the principal surface of the SiC substrate.