SiC Single Crystal Dislocation Reduction via Alternating Growth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge is to reduce the high dislocation density, particularly of basal plane dislocations and threading edge dislocations, in SiC single crystals to achieve low power loss and high-performance SiC semiconductor devices, as conventional methods fail to effectively minimize these dislocations without increasing others, leading to increased leak current and reduced withstand voltage.
Innovation Solution
The method involves growing SiC single crystals using a repeated a-face (a-plane) growth (RAF) method, where a c-plane growth substrate with a large offset angle is used to generate screw dislocations on one side and a substrate with a small offset angle on the other side, allowing dislocations to be discharged without converting, resulting in a low combined density of basal plane and threading edge dislocations, thereby reducing impurity levels in the epitaxial layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional c-plane or a-plane growth methods are used, then SiC single crystals can be obtained, but the dislocation density remains high and cannot be effectively reduced
Solution Approach 1:
The crystal growth process is segmented into multiple alternating stages: a-plane growth followed by c-plane growth, repeated multiple times. Each stage targets specific dislocation types, progressively reducing overall dislocation density through sequential purification rather than attempting single-stage reduction of all dislocation types simultaneously
Solution Approach 2:
The patent employs periodic alternation between a-plane growth and c-plane growth modes. During a-plane growth, basal plane dislocations are reduced; during c-plane growth, threading edge dislocations are reduced. This periodic switching creates a rhythm of dislocation type-specific elimination that progressively purifies the crystal
2Ease of manufacture
If dislocation density is high, then crystal growth is easier to achieve, but device performance deteriorates with increased leak current and reduced withstand voltage
Solution Approach 1:
The patent changes the growth parameters by alternating between different crystal plane orientations (a-plane and c-plane) and adjusting growth conditions for each stage. This parameter variation enables progressive dislocation reduction while maintaining crystal growth feasibility, ultimately achieving the ultra-low dislocation density of 10^6 cm^-2 or less required for high-performance devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the density of threading dislocations in the epitaxial layer, enabling the manufacture of high-performance SiC devices with reduced leak current and improved withstand voltage, as demonstrated by achieving dislocation densities below 3,700 cm/cm3, which is not attainable with conventional methods.
Implementation Method 1
growing an SiC single crystal over the growth plane by a sublimation reprecipitation method
Implementation Method 2
reducing impurity levels in the epitaxial layer
Data Source
AI summary
An SiC single crystal includes a low dislocation density region (A) where the density of dislocations each of which has a Burgers vector in a {0001} in-plane direction (mainly a direction parallel to a <11-20> direction) is not more than 3,700 cm/cm3. Such an SiC single crystal is obtained by: cutting out a c-plane growth seed crystal of a high offset angle from an a-plane grown crystal; applying c-plane growth so that the density of screw dislocations introduced into a c-plane facet may fall in a prescribed range; cutting out a c-plane growth crystal of a low offset angle from the obtained c-plane grown crystal; and applying c-plane growth so that the density of screw dislocations introduced into a c-plane facet may fall in a prescribed range. An SiC wafer and a semiconductor device are obtained from such an SiC single crystal.