4H-SiC Substrate Defect Reduction for High Voltage Devices
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Solution Overview
Problem
High power semiconductor devices fabricated on silicon carbide substrates face performance limitations due to significant concentrations of micropipes, screw dislocations, and basal plane dislocations, which are challenging to reduce simultaneously using existing techniques, especially when operating at high voltages.
Innovation Solution
The development of a 4H-SiC substrate with reduced micropipe, screw dislocation, and basal plane dislocation densities, combined with epitaxial layers having controlled net carrier concentration and low defect densities, achieved through optimized CVD epitaxy processes and substrate preparation methods, allowing for the formation of high voltage semiconductor devices with improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SiC substrate growth methods are used, then substrate production is achieved, but high concentrations of micropipes, screw dislocations, and basal plane dislocations are present
Solution Approach 1:
The patent applies preliminary action by performing substrate preparation treatments before epitaxial layer formation. Specifically, the substrate undergoes chemical etching and/or mechanical polishing to remove or reduce defect concentrations at the substrate surface prior to growing the epitaxial layers, preventing defect propagation into the active device regions
Solution Approach 2:
The patent segments the defect reduction process into multiple independent steps: (1) chemical etching to remove surface defects, (2) mechanical polishing to reduce dislocation densities, and (3) controlled epitaxial growth. This segmentation allows each step to target specific defect types and achieve cumulative defect reduction
2Manufacturing precision
If existing defect reduction techniques are applied, then one type of defect may be reduced, but other defect types remain significant
Solution Approach 1:
The patent employs parameter changes by systematically varying etching conditions (chemical composition, temperature, time) and polishing parameters (pressure, speed, abrasive type) to optimize defect reduction for different defect types. This allows tailored reduction of micropipes, screw dislocations, and basal plane dislocations through parameter optimization
3Power
If high voltage operation is designed, then power performance is enhanced, but defect effects become more pronounced
Solution Approach 1:
The patent applies the extraction principle by removing defective regions from the substrate before device fabrication. Through selective etching and polishing, micropipes and high-density dislocation regions are extracted or removed, leaving a cleaner substrate base for growing high-quality epitaxial layers that can support high voltage operation without defect-related performance degradation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in semiconductor devices with enhanced reverse voltage blocking capabilities, approaching 85-95% of theoretical values, and reduced defect propagation from substrates to epitaxial layers, thereby improving the operational performance and stability of high voltage devices.
Implementation Method 1
optimized CVD epitaxy processes
Data Source
AI summary
4H SIC epiwafers with thickness of 50-100 μm are grown on 4° off-axis substrates. Surface morphological defect density in the range of 2-6 cm−2 is obtained from inspection of the epiwafers. Consistent carrier lifetime in the range of 2-3 μs has been obtained on these epiwafers. Very low BPD density has been confirmed in the epiwafers with BPD density down to below 10 cm−2. Epitaxial wafers with thickness of 50-100 μm have been used to fabricate diodes. High voltage testing has demonstrated blocking voltages near the theoretical values for 4H-SiC. Blocking voltage as high as 8 kV has been achieved in devices fabricated on 50 μm thick epitaxial films, and blocking voltage as high as 10 kV has been obtained in devices fabricated on 80 μm thick films. Failure analysis confirmed triangle defects, which form from surface damage or particles present during epitaxy, are killer defects and cause the device to fail in reverse bias operation. In addition, the leakage current at the high blocking voltages of the JBS diodes showed no correlation with the screw dislocation density. It is also observed that the main source of basal plane dislocations in the epilayer originates in the crystal growth process.