SiC Defect Suppression Layer for Dislocation Control
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Solution Overview
Problem
Semiconductor devices with silicon carbide (SiC) substrates suffer from basal plane dislocations that lead to characteristic fluctuations and increased loss, reducing their long-term reliability due to the extension of dislocations during operation, especially in bipolar modes.
Innovation Solution
A semiconductor device structure and manufacturing method that includes a defect suppression layer with higher lattice strain, formed by ion implantation, to suppress the extension of basal plane dislocations and maintain breakdown voltage and on-voltage over time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If silicon carbide (SiC) is used as the semiconductor material, then breakdown voltage and on-resistance are improved, but basal plane dislocations occur and extend during operation, reducing long-term reliability
Solution Approach 1:
The patent applies preliminary action by forming a defect suppression layer before the dislocation extension problem occurs during device operation. This layer is created through ion implantation into the drift region, introducing lattice strain that proactively prevents basal plane dislocation extension before it can degrade device performance over time.
Solution Approach 2:
The patent changes the physical parameter of the semiconductor structure by introducing lattice strain through ion implantation. This modifies the stress state in the drift region, creating a compressed or strained environment that counteracts the tensile stress that would otherwise cause basal plane dislocations to extend during bipolar operation.
2Ease of manufacture
If basal plane dislocations are present in the semiconductor substrate, then device manufacturing is simplified, but dislocation extension occurs during bipolar operation, causing characteristic fluctuation and increased loss
Solution Approach 1:
The patent applies local quality by creating a defect suppression layer specifically in the drift region where basal plane dislocations are most problematic during bipolar operation. The ion implantation is targeted at this specific area, introducing lattice strain locally to suppress dislocation extension without affecting other regions of the device, thus preventing energy loss while maintaining overall device functionality.
3Device complexity
If no defect suppression layer is formed, then device structure is simpler, but stacking faults occur and breakdown voltage degrades over time
Solution Approach 1:
The patent applies preliminary action by forming the defect suppression layer through ion implantation before the device is put into operation. This proactive measure introduces lattice strain that will suppress stacking fault formation and prevent breakdown voltage degradation throughout the device's operational lifetime, ensuring long-term stability without adding complex operational requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The defect suppression layer effectively reduces the occurrence of stacking faults and maintains the breakdown voltage and on-voltage for a long period, enhancing the reliability of SiC-based semiconductor devices.
Implementation Method 1
a lattice strain of the fourth semiconductor region being greater than a lattice strain of the third semiconductor region
Implementation Method 2
forming a fourth semiconductor region by performing ion implantation into the third semiconductor region
Data Source
AI summary
According to one embodiment, a semiconductor device, includes: a first semiconductor region of a first conductivity type; a second semiconductor region provided on the first semiconductor region, an impurity concentration of the second semiconductor region being lower than an impurity concentration of the first semiconductor region; a third semiconductor region of a second conductivity type provided on the second semiconductor region; and a fourth semiconductor region provided on the third semiconductor region or in a portion of the third semiconductor region. A lattice strain of the fourth semiconductor region is greater than a lattice strain of the third semiconductor region.