SiC Device Outer Cell Area Reduction for Stacking Fault Prevention
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices face challenges in maintaining current carrying capability while inhibiting the formation of stacking faults, as previous methods either reduce current carrying capacity or increase production complexity and costs.
Innovation Solution
A silicon carbide semiconductor device with a specific cell structure arrangement, where the outermost peripheral cells have a reduced surface area and lower impurity concentration compared to inner peripheral cells, reducing current concentration and recombination of electron-hole pairs, thereby inhibiting stacking fault formation without forming current-limiting or fault stop regions within the active area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stripe-shaped current-limiting regions are formed extending parallel to the principal surface of the silicon carbide substrate between the base regions of adjacent cells, then stacking fault expansion is prevented, but current carrying capability is reduced
Solution Approach 1:
The invention applies local quality by forming current-limiting regions with different impurity concentrations in specific locations. The first current-limiting regions have a first impurity concentration while the second current-limiting regions have a second impurity concentration that is lower than the first. This local variation in impurity concentration allows different parts of the device to have different electrical properties, enabling stacking fault prevention in specific areas while maintaining current carrying capability in other areas.
Solution Approach 2:
The invention changes the impurity concentration parameter of the current-limiting regions to resolve the contradiction. By setting the impurity concentration of the second current-limiting regions to be lower than that of the first current-limiting regions, the electrical characteristics are adjusted locally. This parameter change allows the device to prevent stacking faults where needed while maintaining adequate current carrying capability in regions with lower impurity concentration.
2Reliability
If fault stop regions with trench-shaped grooves are formed dividing the epitaxial growth layer, then stacking fault expansion is prevented, but device complexity and manufacturing cost increase
Solution Approach 1:
The invention extracts the essential function of fault stop regions (preventing stacking fault expansion) without requiring the complex trench-shaped groove structure. Instead of forming deep trenches that divide the epitaxial growth layer, the invention uses simpler current-limiting regions with adjusted impurity concentrations that achieve the same fault prevention effect with reduced structural complexity and manufacturing steps.
Solution Approach 2:
The invention changes the approach from structural modification (trenches) to parameter modification (impurity concentration). By adjusting the impurity concentration in the current-limiting regions rather than forming physical trenches, the invention achieves stacking fault prevention with simpler device structure and reduced manufacturing complexity.
3Reliability
If current-limiting regions are selectively buried in the epitaxial growth layer, then stacking fault expansion is stopped, but current carrying capability is reduced
Solution Approach 1:
The invention applies local quality by creating current-limiting regions with different impurity concentrations in specific locations rather than uniformly burying current-limiting regions throughout the device. The first current-limiting regions have higher impurity concentration for effective fault stopping, while the second current-limiting regions have lower impurity concentration to maintain current carrying capability. This spatially differentiated approach resolves the contradiction between fault prevention and current conduction.
Solution Approach 2:
The invention changes the impurity concentration parameter of the current-limiting regions to optimize both stacking fault prevention and current carrying capability. By setting different impurity concentrations in different current-limiting regions rather than using a uniform concentration, the invention achieves effective fault stopping where needed while maintaining adequate current conduction in other areas.
Data Source
AI summary
An embodiment of a silicon carbide semiconductor device includes one or more inner cells each having a MOSFET and one or more outer peripheral cells that does not have a MOSFET structure, and the area (surface area) of the p+ contact region of each of the outermost peripheral cells is less than the surface area of an p+ contact region of each of the inner cells, for example, so that a unit total resistance of p+ contact regions of the outermost peripheral cells, as measured in a depth direction of the semiconductor substrate with respect to a unit area in a surface of the semiconductor substrate, is greater than a unit total resistance of the p+ contact regions of the inner cells, as measured in the depth direction of the semiconductor substrate with respect to the unit area in the surface of the semiconductor substrate.