SiC Semiconductor Device with Depletion and Gate Channel Control
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Solution Overview
Problem
Silicon carbide semiconductor devices with normally-off characteristics and low ON resistance are difficult to achieve using a single chip due to the challenges of high-speed operation and increased size and manufacturing costs associated with multi-chip configurations.
Innovation Solution
A silicon carbide semiconductor device is designed with a silicon carbide substrate having multiple conductivity type layers and impurity regions, along with a gate insulating film, allowing for coordinated channel control using both depletion layers and insulated gates, enabling high-speed operation and normally-off characteristics while being configured on a single substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cascode configuration using two chips (SiC VJFET and Si MOSFET) is used to achieve normally-off characteristics, then normally-off characteristics are achieved, but device size and manufacturing cost increase
Solution Approach 1:
The patent merges the VJFET and MOSFET functionalities into a single integrated device structure on one SiC substrate. The device combines a first conductivity type drift layer with second conductivity type impurity regions, creating an integrated structure that provides both the high-speed low-resistance characteristics of junction transistors and the normally-off characteristics of insulated gate transistors, eliminating the need for separate cascode chips
Solution Approach 2:
The single chip device performs multiple functions simultaneously: it provides high-speed switching operation like a junction transistor, maintains low ON resistance, and achieves normally-off characteristics like an insulated gate transistor. This multi-functionality is achieved through the coordinated channel control mechanism using both depletion layers and insulated gates within one integrated structure
2Device complexity
If a single chip configuration is used to reduce device size and manufacturing cost, then device size and manufacturing cost are reduced, but achieving both normally-off characteristics and low ON resistance with high-speed operation becomes difficult
Solution Approach 1:
The patent applies different conductivity types in specific local regions of the device structure. Second conductivity type impurity regions are selectively formed in the first conductivity type drift layer at specific locations to create localized channel control regions. This local differentiation enables coordinated channel control that achieves normally-off characteristics while maintaining low ON resistance and high-speed operation capabilities
Solution Approach 2:
The device utilizes a composite structure combining first conductivity type and second conductivity type regions within the SiC substrate. This composite doping structure creates multiple functional zones that work together to achieve the triple benefit of normally-off characteristics, low ON resistance, and high-speed operation in a single integrated device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves high-speed operation with low ON resistance and normally-off characteristics, reducing manufacturing costs by eliminating the need for multiple chips and simplifying the manufacturing process.
Implementation Method 1
channel control utilizing a depletion layer in a pn junction between the first layer and the third impurity region
Implementation Method 2
channel control utilizing an insulated gate over the second layer
Data Source
AI summary
First, second, fourth, and fifth impurity regions have a first conductivity type, and a third impurity region has a second conductivity type. The first to third impurity regions reach a first layer having the first conductivity type. The fourth and fifth impurity regions are provided on a second layer. First to fifth electrodes are provided on the first to fifth impurity regions, respectively. Electrical connection is established between the first and fifth electrodes, and between the third and fourth electrodes. A sixth electrode is provided on a gate insulating film covering a portion between the fourth and fifth impurity regions.