SiC Device Dual Parallel PN Layer Termination
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional silicon carbide semiconductor devices with a super junction (SJ) structure have a low breakdown voltage in the edge termination region compared to the active and intermediate regions, leading to facilitated avalanche breakdown and reduced overall avalanche capability.
Innovation Solution
The silicon carbide semiconductor device incorporates a dual parallel pn layer structure, where the second parallel pn layer in the edge termination region is positioned deeper and apart from the first parallel pn layer, with the p-type regions of the second parallel pn layer being wider and closer to the chip end, enhancing the breakdown voltage by suppressing electric field concentration and avalanche breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single parallel pn layer structure is used in the edge termination region, then the device structure remains simple, but the breakdown voltage is low and avalanche breakdown is facilitated
Solution Approach 1:
The drift layer is divided into two separate parallel pn layers (first and second) positioned at different depths within the semiconductor substrate. This segmentation allows each layer to contribute differently to the electric field distribution, with the first layer closer to the surface and the second layer deeper, creating a more distributed voltage breakdown profile that enhances overall breakdown voltage in the edge termination region
Solution Approach 2:
The invention transitions from a single-plane (2D) parallel pn layer structure to a multi-depth (3D) structure by positioning the first and second parallel pn layers at different depths within the semiconductor substrate. This vertical dimensionality addition creates a three-dimensional electric field distribution that suppresses electric field concentration at the surface, thereby enhancing breakdown voltage and avalanche capability
2Reliability
If the second parallel pn layer is positioned deeper and apart from the first parallel pn layer, then electric field concentration is suppressed and breakdown voltage increases, but the device structure becomes more complex
Solution Approach 1:
The first and second parallel pn layers are nested within the semiconductor substrate at different depths, with the first layer positioned closer to the surface and the second layer positioned deeper. This nested arrangement allows both layers to coexist within the same substrate volume, creating a distributed electric field management system that enhances avalanche capability while utilizing the available substrate depth efficiently
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly enhances the breakdown voltage and avalanche capability of the edge termination region, bringing it closer to the active region's breakdown voltage, thereby improving the overall performance of the silicon carbide semiconductor device.
Implementation Method 1
enhancing the breakdown voltage by suppressing electric field concentration
Implementation Method 2
suppressing electric field concentration and avalanche breakdown
Data Source
AI summary
A silicon carbide semiconductor device, including a semiconductor substrate having an active region and a termination region that surrounds the active region in a top view, a first parallel pn layer provided in the semiconductor substrate in the active region, a second parallel pn layer provided in the semiconductor substrate in the termination region, a device structure provided in the active region, a first electrode electrically connected to the device structure, a second electrode, a first semiconductor region selectively provided in the termination region, and a second semiconductor region provided between the second parallel pn layer and the first semiconductor region, and in contact with the first semiconductor region. The second parallel pn layer is provided apart from the first semiconductor region, at a position deeper than the first semiconductor region and closer to an end of the semiconductor substrate than an outer end of the first semiconductor region.