SiC Device Impurity Geometry for ON Resistance and Field Control
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Solution Overview
Problem
Silicon carbide semiconductor devices face challenges in managing electric field concentration and ON resistance, particularly in termination regions where high electric field intensities lead to increased ON resistance due to the geometry of gate trenches and impurity regions.
Innovation Solution
The silicon carbide semiconductor device incorporates a specific geometry for the impurity regions and gate trenches, with varying spacings and widths between different impurity regions and the main surface to alleviate electric field concentration and reduce ON resistance by optimizing the current path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate trench geometry and impurity region configuration are optimized to reduce ON resistance, then the current path is improved, but electric field concentration increases in the termination region
Solution Approach 1:
The patent applies local quality by creating different impurity region configurations at different locations: the first impurity region is positioned closer to the gate trench in the active region to reduce ON resistance, while the second impurity region is positioned farther away in the termination region to prevent electric field concentration. This spatial differentiation of impurity distribution optimizes both conductivity and electric field management in their respective zones.
Solution Approach 2:
The patent segments the impurity regions into distinct zones: a first impurity region adjacent to the gate trench bottom surface in the active region, and a second impurity region in the termination region at a different spacing. This segmentation allows independent optimization of each region's function - one for low resistance and the other for electric field control - resolving the contradiction between these competing requirements.
2Reliability
If the spacing between impurity regions and gate trench is reduced to improve current flow, then ON resistance decreases, but electric field intensity increases in termination regions
Solution Approach 1:
The patent implements local quality by specifying different spacing distances for impurity regions based on their location: the first impurity region in the active region has a smaller spacing to the gate trench bottom surface to enhance current flow and reduce ON resistance, while the second impurity region in the termination region has a larger spacing to reduce electric field intensity and prevent premature breakdown.
Data Source
AI summary
The side surface has a first outer end surface. The bottom surface has a first bottom portion continuous to the first outer end surface, and a second bottom portion continuous to the first bottom portion and located on a side opposite to the inner end surface with respect to the first bottom portion. A silicon carbide substrate has a first region and a second region located between the at least one gate trench and a second main surface, and spaced from each other with a drift region being sandwiched therebetween. In a direction parallel to the first outer end surface, a spacing between the first region and the second region located between the first bottom portion and the second main surface is smaller than a spacing between the first region and the second region located between the second bottom portion and the second main surface.