SiC Semiconductor Device Reducing ON Resistance
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Solution Overview
Problem
In high-voltage semiconductor devices, such as those operating at 10 kV or greater, the presence of electrically active defects like carbon vacancies near the pn junction interface hampers minority carrier injection, leading to increased ON resistance due to unipolar conduction and reduced conductivity modulation effects.
Innovation Solution
A method involving ion implantation of impurity ions and interstitial carbon ions into a silicon carbide semiconductor substrate to form a surplus carbon region deeper than the pn junction interface, followed by heating to activate the impurities and disperse interstitial carbon atoms, thereby reducing carrier traps and enhancing minority carrier injection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a drift layer with low concentration and great thickness is used to maintain withstand pressure in extra-high-voltage region, then the device can operate at high voltage, but drift resistance and ON resistance increase
Solution Approach 1:
The patent changes the electrical parameters of the drift layer by introducing bipolar device characteristics (pn junction structure) to modify carrier conduction behavior. This transforms the drift layer from unipolar conduction to bipolar conduction, reducing ON resistance while maintaining high voltage withstand capability through conductivity modulation effects
Solution Approach 2:
The patent creates a composite structure combining p-type and n-type regions within the drift layer to form a bipolar device. This composite structure enables both high voltage blocking capability (from the drift layer) and low ON resistance (from the bipolar conduction mechanism with both electrons and holes contributing to current flow)
2Reliability
If the lifetime of carriers is extended to enhance conductivity modulation effects, then ON resistance is reduced, but switching characteristics deteriorate and switching loss increases
Solution Approach 1:
The patent optimizes the carrier lifetime parameter to an appropriate intermediate value that balances conductivity modulation benefits with switching performance requirements. By controlling lifetime through defect management, the device achieves sufficient conductivity modulation for low ON resistance while maintaining acceptable switching characteristics
Solution Approach 2:
The patent creates dynamic control over carrier behavior through the pn junction structure, allowing the device to exhibit conductivity modulation during forward conduction (reducing ON resistance) while enabling effective carrier removal during switching transitions (reducing switching loss). The bipolar mechanism provides dynamic adaptability between conduction and switching states
3Ease of manufacture
If electrically active defects such as carbon vacancies are present near the pn junction interface, then the device structure is simpler, but minority carrier injection is hampered and ON resistance increases
Solution Approach 1:
The patent converts the harmful effect of carbon vacancies and other defects near the pn junction interface into a beneficial outcome by using them as targets for interstitial carbon atom filling. The defects that would normally act as recombination centers are transformed into sites for improving material quality, reducing carrier traps, and enhancing minority carrier injection efficiency
Solution Approach 2:
The patent introduces interstitial carbon atoms as an intermediary substance that mediates between the existing carbon vacancies/defects and the desired improved electrical characteristics. These interstitial carbon atoms fill the vacancy sites, passivate defect states, and eliminate recombination centers, thereby improving minority carrier injection without requiring complete restructuring of the device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces ON resistance by minimizing carrier traps near the pn junction interface, improving conductivity modulation and switching characteristics in high-voltage semiconductor devices.
Implementation Method 1
an ion implanted layer formation step of implanting impurity ions being impurities of a second conductivity type in a surface of the drift layer to form an ion implanted layer in which the impurity ions are implanted
Implementation Method 2
a surplus carbon region formation step of implanting interstitial carbon inducing ions that induce carbon between lattices in the drift layer to form a surplus carbon region having surplus interstitial carbon atoms
Implementation Method 3
a heating step of heating the drift layer after the ion implanted layer formation step and after the surplus carbon region formation step. The heating step heats the drift layer to activate the impurity ions implanted in the ion implanted layer in order to form an activation layer of the second conductivity type
Implementation Method 4
the heating step heats the drift layer to activate the impurity ions implanted in the ion implanted layer in order to form an activation layer of the second conductivity type while the heating step heats the drift layer to disperse the interstitial carbon atoms toward the activation layer
Data Source
AI summary
A method for manufacturing a semiconductor device capable of reducing an ON resistance. In the present invention, a drift layer is formed on a substrate. An ion implanted layer is formed in a surface of the drift layer. A surplus carbon region is formed in the drift layer. The drift layer is heated. In a case where the surplus carbon region is formed, the surplus carbon region is formed in a region deeper than an interface between the ion implanted layer and the drift layer. In a case where the drift layer is heated, impurity ions of the ion implanted layer are activated to form an activation layer, and interstitial carbon atoms are dispersed toward the activation layer.