SiC Device Source Resistance via P-Type Trench Regions
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices fail to sufficiently achieve the source follower effect due to low source resistance values, leading to inadequate tradeoff between short circuit capability and ON resistance reduction.
Innovation Solution
The silicon carbide semiconductor device incorporates p-type regions between gate insulating films and n-type source regions within trenches, preventing electron accumulation layer connection and reducing contact area, thereby increasing source resistance and enhancing the source follower effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If n-type source resistance regions are provided between n+-type source regions and channels to increase source resistance, then short circuit capability is enhanced, but ON resistance increases
Solution Approach 1:
The patent applies local quality by creating p-type regions with specifically controlled impurity concentrations in localized areas between the gate insulating films and n-type source resistance regions. These p-type regions are positioned only where needed to modulate the electric field and carrier distribution, allowing the source resistance to be increased for short circuit protection while minimizing the impact on ON resistance through precise spatial control of the doping profile.
Solution Approach 2:
The patent utilizes parameter changes by varying the impurity concentration of the p-type regions to optimize the tradeoff between short circuit capability and ON resistance. By controlling the doping concentration of the p-type regions, the electric field distribution and carrier accumulation are adjusted, enabling dynamic control of the source resistance characteristic to achieve both enhanced short circuit capability and acceptable ON resistance.
2Reliability
If source resistance is increased to achieve source follower effect, then short circuit capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the p-type regions with the existing trench gate structure and n-type source resistance regions, integrating multiple functions into a unified structure. The p-type regions are formed within the same trench structure, combining the gate insulation function, the source resistance function, and the electric field modulation function in a single integrated configuration, thereby reducing overall device complexity while achieving the source follower effect.
Solution Approach 2:
The p-type regions serve multiple functions simultaneously: they modulate the electric field to enhance carrier accumulation for the source follower effect, control the source resistance value, and work in conjunction with the gate insulating films to define the channel region. This multi-functionality reduces the need for separate structures and simplifies the overall device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a high source resistance value, effectively achieving the source follower effect, reducing drain-source current, and improving the tradeoff between short circuit capability and ON resistance reduction.
Implementation Method 1
a resistance value of the source resistance Rs is increased, whereby a tradeoff relationship between enhancement of short circuit capability and reduction of ON resistance Ron by a source follower effect is improved
Data Source
AI summary
A silicon carbide semiconductor device, including a semiconductor substrate, and a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions and a plurality of fourth semiconductor regions formed in the semiconductor substrate. The semiconductor device further includes a plurality of trenches penetrating the second, third and fourth semiconductor regions, a plurality of gate electrodes respectively provided via a plurality of gate insulating films in the trenches, a plurality of fifth semiconductor regions each provided between one of the gate insulating films at the inner wall of one of the trenches, and the third semiconductor region and the fourth semiconductor region through which the one trench penetrates. The semiconductor device further includes first electrodes electrically connected to the second, third and fourth semiconductor regions, and a second electrode provided on a second main surface of the semiconductor substrate.