SiC Semiconductor Element Thinning via Dicing Grooves
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Solution Overview
Problem
Silicon carbide semiconductor devices face challenges in reducing on-resistance while maintaining substrate strength and preventing wafer cracking, particularly when thinning the substrate to achieve lower on-resistance, as existing thinning methods like RIE, sandblasting, and FIB are inefficient or impractical.
Innovation Solution
Forming slit-shaped grooves on the backside of the semiconductor substrate using a dicing saw, with the grooves extending from one end and spaced closer than the dicing blade width, followed by RIE and sacrificial oxidation to remove damage and thin the substrate surface, thereby reducing substrate resistance without compromising mechanical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the substrate thickness is reduced to lower substrate resistance, then the on-resistance decreases, but the mechanical strength deteriorates and wafer cracking occurs
Solution Approach 1:
The substrate is segmented into multiple regions by forming slit-shaped grooves that extend from the front surface to the back surface. These grooves divide the substrate into isolated islands, reducing the effective substrate thickness in the active regions and thereby lowering the substrate resistance and on-resistance while maintaining adequate mechanical strength in the remaining substrate portions.
2Loss of energy
If conventional thinning methods (RIE, sandblasting, FIB) are used to reduce substrate thickness, then the substrate resistance decreases, but the manufacturing efficiency deteriorates and the process becomes impractical
Solution Approach 1:
Conventional thinning methods using RIE, sandblasting, or FIB are replaced with a mechanical dicing method. Slit-shaped grooves are formed by dicing the substrate from the back surface using a dicing saw, which is a highly efficient mechanical process suitable for mass production. This substitution dramatically improves manufacturing efficiency while achieving the same goal of reducing substrate resistance.
3Loss of energy
If the substrate is thinned to reduce on-resistance, then the electrical performance improves, but the reliability deteriorates due to increased susceptibility to damage
Solution Approach 1:
The substrate is subjected to localized thinning only in the element formation regions where low resistance is needed. The slit-shaped grooves are formed specifically in these regions, creating local quality changes that reduce substrate resistance where required while leaving other substrate regions intact to maintain overall structural integrity and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces substrate resistance by up to 0.5 mΩcm² and achieves a voltage reduction of about 0.2 V at a current density of 400 A/cm², enhancing the forward characteristics of silicon carbide semiconductor elements.
Implementation Method 1
forming slit-shaped grooves on the backside of the semiconductor substrate using a dicing saw
Implementation Method 2
followed by RIE and sacrificial oxidation to remove damage and thin the substrate surface
Implementation Method 3
followed by RIE and sacrificial oxidation to remove damage and thin the substrate surface
Data Source
AI summary
In a fabrication method of a silicon carbide semiconductor element including a drift layer playing a role of retaining a high withstand voltage on a front side of a semiconductor substrate of silicon carbide and including an ohmic electrode on a backside, dicing is added to form at least one dicing line in an element active region on a surface of the semiconductor substrate on a side opposite of the drift layer before forming the ohmic electrode on the backside of the semiconductor substrate. Thus, a silicon carbide semiconductor element and fabrication method thereof is provided such that even if the semiconductor substrate is made thinner to reduce the on-resistance, the strength of the substrate can be maintained and cracking of the wafer during wafer processing can be reduced.