SiC Schottky Diode Gate-Controlled Barrier
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Solution Overview
Problem
Silicon carbide (SiC) power semiconductor devices face challenges with high Schottky barrier heights leading to increased ON voltage and energy loss, and limited flexibility in forming a desired Schottky barrier, which also results in inadequate suppression of backward leakage current.
Innovation Solution
A semiconductor device configuration with a Schottky substitute diode and PiN diode portions, where the impurity concentration and thickness of p-type layers are selectively controlled to adjust the energy barrier height and extend the depletion layer, allowing for a lower ON voltage while maintaining a high withstand voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a Schottky barrier diode is formed using conventional electrode materials and heat treatment, then a Schottky junction is formed, but the Schottky barrier height is high leading to increased ON voltage and energy loss
Solution Approach 1:
The patent changes the fundamental parameter of barrier formation from thermal Schottky barrier (dependent on work function difference) to field-induced barrier (MOS structure). By introducing a gate electrode and dielectric layer, the barrier height is controlled by applied voltage rather than material properties, enabling dynamic adjustment of ON voltage and reducing energy loss
Solution Approach 2:
A dielectric layer is introduced as an intermediary between the semiconductor substrate and gate electrode. This dielectric layer enables field effect control of the Schottky barrier, allowing the barrier height to be modulated by the gate voltage without direct metal-semiconductor contact, thus reducing ON voltage and energy loss
2Reliability
If the Schottky barrier height is decreased to lower ON voltage, then forward characteristics improve, but backward leakage current increases
Solution Approach 1:
The patent implements dynamic control of the Schottky barrier height through gate voltage adjustment. The barrier can be lowered during forward conduction to reduce ON voltage, and raised during reverse bias to suppress leakage current. This dynamic modulation resolves the contradiction between forward and reverse characteristics
Solution Approach 2:
The gate electrode provides feedback control of the Schottky barrier height. By monitoring the operational state (forward or reverse bias), the gate voltage can be adjusted to maintain optimal barrier height, suppressing leakage current during reverse bias while enabling low ON voltage during forward conduction
3Adaptability or versatility
If various electrode materials are examined to select a wider range of Schottky barrier heights, then material options increase, but a desired Schottky barrier is not always obtained and the process becomes complex
Solution Approach 1:
The patent replaces the material-based Schottky barrier formation (dependent on work function differences between specific metal and semiconductor materials) with a field-effect-based barrier control using a MOS structure. This substitution provides continuous可调 range of barrier heights without being constrained by discrete material combinations, simplifying the design process while enhancing adaptability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves a low-loss semiconductor device with controlled ON voltage and suppressed backward leakage current, maintaining the basic diode characteristics.
Implementation Method 1
a backward leakage current is suppressed by a depletion layer spreading from a (p+) SiC portion of a PN diode to an (n−) SiC epitaxial growth layer
Data Source
AI summary
A semiconductor device according to an embodiment includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the second conductivity type, a first electrode and a second electrode. The first semiconductor region is formed on at least a part of the first semiconductor layer formed on the semiconductor substrate. The second semiconductor region is formed on another part of the first semiconductor layer to reach an inside of the first semiconductor layer and having an impurity concentration higher than that of the first semiconductor region. The first electrode is formed on the second semiconductor region and a third semiconductor regions formed in a part of the first semiconductor region. The second electrode is formed to be in contact with a rear surface of the semiconductor substrate.