SiC Planar Gate DMOSFET Source Layout for Higher Cross Over Current
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Solution Overview
Problem
Silicon carbide (SiC) power MOSFETs face reliability issues due to challenges in inversion-layer mobility and passivating dielectric layers, along with limitations in third quadrant cross over current, which affect performance and reliability in power electronics applications.
Innovation Solution
A vertical Silicon Carbide (SiC) double-implantation metal oxide semiconductor field-effect transistor (DMOSFET) design is implemented, featuring a first conductivity type second source region with a thickness and doping concentration optimized between the silicide layer and the second conductivity type well region, and a second conductivity type well contact region that meanders to enhance third quadrant cross over current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional SiC power MOSFET design is used, then the device can handle high power levels, but the third quadrant cross over current is limited and reliability issues occur
Solution Approach 1:
The source region is divided into two distinct parts: a first source region with higher doping concentration and a second source region with lower doping concentration. This segmentation allows the first source region to provide low ON resistance while the second source region enables higher cross over current by controlling minority carrier injection, thus resolving the contradiction between reliability and power handling in the third quadrant.
Solution Approach 2:
Different regions of the device are assigned different doping concentrations to optimize local functions. The first source region has higher doping for low resistance conduction, while the second source region has lower doping to reduce minority carrier injection and increase cross over current. This local differentiation allows simultaneous optimization of both reliability and third quadrant power capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The optimized DMOSFET design increases third quadrant cross over current by tuning the turn-on voltage and reducing minority carrier injection, thereby improving device reliability and reducing differential ON resistance, mitigating basal plane dislocation issues.
Implementation Method 1
forming a second conductivity type well region by performing a second conductivity type implantation through a first patterned hard mask layer on the SiC substrate, forming a first conductivity type source region by performing a first conductivity type implantation through a second patterned hard mask layer on the SiC substrate
Data Source
AI summary
An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N− drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.