SiC DMOSFET Gate Reliability via Sinker Field Redistribution
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Solution Overview
Problem
Silicon carbide (SiC) power MOSFETs face reliability issues due to high electric field concentrations in the gate oxide, leading to Fowler-Nordheim tunneling currents and trapped charge, as well as challenges in manufacturing processes like ion implantation, which result in misalignment and asymmetry in MOS channel lengths, affecting ON resistance and threshold voltage.
Innovation Solution
The introduction of deep P-type Sinker regions and a trench structure in the SiC DMOSFET design, which redistributes the electric field away from the gate oxide, reduces the electric field concentration, and employs self-aligned manufacturing techniques to minimize misalignment and enhance channel length uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional ion implantation processes are used for manufacturing SiC devices, then source and p-well regions can be formed, but misalignment and asymmetry in MOS channel lengths occur, affecting ON resistance and threshold voltage
Solution Approach 1:
The patent applies preliminary action by forming the p-well region first, then using its sidewalls as alignment references for subsequent source region formation. This preliminary structuring ensures that the source regions are automatically aligned to the p-well, eliminating misalignment issues that would otherwise occur with conventional separate implantation processes
Solution Approach 2:
The patent introduces sidewall spacers as an intermediary element between the p-well region and the source region. These spacers serve as a physical mediator that defines the precise location and dimensions of the source regions, ensuring uniform MOS channel lengths without requiring high-precision direct alignment of implantation steps
2Reliability
If deep ion implantation is performed in SiC to form source and p-well regions, then the required doping profiles can be achieved, but the process becomes extremely difficult and time-consuming
Solution Approach 1:
The patent segments the doping process into multiple shallower implantation steps rather than attempting a single deep implantation. By dividing the total doping depth into sequential stages with intermediate annealing steps, the process achieves the required deep doping profiles while maintaining manufacturing feasibility and reducing process complexity
Solution Approach 2:
The patent maintains continuity of useful action by performing multiple implantation and annealing cycles in sequence, continuously building up the doping profile to the required depth. This continuous progressive doping approach is more efficient than attempting to achieve the full depth in a single step, which would require extremely high energy and result in poor process control
3Manufacturing precision
If the p-well and N+ source regions are formed using different masks, then the MOS channel length can be controlled, but mask misalignment results in different channel lengths on each side of the cell
Solution Approach 1:
The patent applies self-service by designing the process so that the p-well sidewalls themselves serve as the alignment reference for source region formation. The structure serves its own alignment function, eliminating the need for external mask alignment and the associated misalignment errors that would create asymmetry in channel lengths
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a breakdown voltage of over 1450V, an ON-resistance of less than 3 milliohm-cm², and a gate threshold voltage greater than 2.8V, while maintaining a low electric field in the gate insulator, improving device reliability and performance.
Implementation Method 1
The introduction of deep P-type Sinker regions and a trench structure in the SiC DMOSFET design, which redistributes the electric field away from the gate oxide, reduces the electric field concentration
Implementation Method 2
SiC devices are manufactured by ion implantation of both source and p-well regions
Data Source
AI summary
An embodiment relates to a device comprising a unit cell on a SiC substrate, the unit cell comprising a gate insulator film, a trench in the well region, and a first sinker region of a second conduction type, wherein the first sinker region has a depth that is equal to or greater than a depth of a well region; wherein the device has an on-resistance of less than 3 milliohm-cm2, a gate threshold voltage of greater than 2.8V, a breakdown voltage of greater than 1450V, and an electric field of less than 3.5 megavolt/cm in the gate insulator film at a drain voltage of less than or equal to 1200 V.