SiC DMOSFET Sinker Field Shielding
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Solution Overview
Problem
SiC power MOSFETs face reliability issues due to high electric field concentration in the gate oxide, leading to Fowler-Nordheim tunneling currents and trapped charge, which are not adequately addressed by conventional manufacturing processes like dopant diffusion, as ion implantation is challenging and inefficient in SiC.
Innovation Solution
The introduction of deep P-type Sinker regions, such as PS #1 and PS #2, which redistribute the electric field away from the gate oxide, combined with a trench in the N+ source region to deepen the PS #1 region, effectively shielding the gate oxide from high electric fields and reducing the electric field concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional dopant diffusion processes are used, then manufacturing is simple, but diffusion coefficients in SiC are negligible at temperatures below 1800°C making the process ineffective
Solution Approach 1:
The patent replaces thermal diffusion (heat-based process) with ion implantation (particle-based process) to introduce dopants into SiC. This substitution allows dopant introduction at lower temperatures where thermal diffusion is negligible, resolving the contradiction between manufacturing simplicity and process effectiveness.
Solution Approach 2:
The patent changes the fundamental parameter of dopant introduction from thermal activation to kinetic impact. By using ion implantation with controlled energy and dose parameters, the process achieves effective dopant introduction in SiC without requiring temperatures above 1800°C, thus maintaining manufacturing feasibility while improving productivity.
2Manufacturing precision
If deep ion implantation is performed in SiC, then source and p-well regions can be formed, but the process is difficult and inefficient
Solution Approach 1:
The patent introduces a temporal dimension to the implantation process by using sequential implantation steps with intermediate thermal annealing. This multi-stage approach breaks down the difficult deep implantation into manageable steps, improving precision while reducing overall process difficulty.
Solution Approach 2:
The patent performs preliminary low-energy implantation followed by thermal annealing to create a foundation for subsequent high-energy deep implantation. This preliminary action prepares the SiC lattice to better accept deep dopant ions, reducing the difficulty of the final deep implantation step while maintaining precision.
3Device complexity
If high electric field concentration is allowed in gate oxide, then device structure is simple, but Fowler-Nordheim tunneling currents and trapped charge occur reducing reliability
Solution Approach 1:
The patent introduces an intermediary P-type sinker region between the high-field drain junction and the gate oxide. This intermediary structure acts as a field-shielding barrier that redistributes the electric field, protecting the gate oxide from direct exposure to high fields while maintaining overall device structural simplicity.
Solution Approach 2:
The patent applies local quality modification by creating a P-type sinker region with specific doping concentration and depth only in critical areas where field redistribution is needed. This localized modification protects the gate oxide from high electric fields without requiring global structural changes, thus maintaining device simplicity while improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces the electric field in the gate oxide to less than 3.5 MV/cm, enhancing device reliability and power conversion efficiency, while minimizing the need for expensive high-energy ion implantation steps and allowing for thinner oxide layers, thus improving the overall performance and longevity of SiC DMOSFETs.
Implementation Method 1
The introduction of deep P-type Sinker regions, such as PS #1 and PS #2, which redistribute the electric field away from the gate oxide
Implementation Method 2
combined with a trench in the N+ source region to deepen the PS #1 region, effectively shielding the gate oxide from high electric fields
Implementation Method 3
SiC has a higher breakdown electric field (3×106 V/cm to 5×106 V/cm) compared to Si (breakdown electric field for Si is 0.3×106 V/cm) and is a better thermal conductor (3.7 (W/cm-K) for SiC versus 1.6 (W/cm-K) for Si)
Data Source
AI summary
An embodiment relates to a device having a SiC substrate, a well region, a source region, and a first sinker region, wherein the first sinker region has a depth that is equal to or greater than a depth of the well region, the source region is within the well region, the first sinker region is within the source region, and the first sinker region is located between a source interconnect metallization region and the SiC substrate. Another embodiment relates to a device having a SiC substrate, a drift layer on the SiC substrate, a well region on the drift layer, a source region within the well region, and a plug within the well region.